An optimization technique for RF buffers with active inductors. - Tai-Cheng Lee; Yen-Chuan Huang (ISCAS (4), 2005)

The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application. - Tai-Cheng Lee; Yen-Chuan Huang (IEEE J. Solid State Circuits, 2006)

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique. - Yen-Chuan Huang; Tai-Cheng Lee (ISSCC, 2010)

A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. - Yen-Chuan Huang; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2010)

A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique. - Yen-Chuan Huang; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. - Chin-Yu Lin; Yen-Chuan Huang; Tai-Cheng Lee (VLSI-DAT, 2013)

10.3 A 12nm CMOS RF Transceiver Supporting 4G/5G UL MIMO. - Ming-Da Tsai; Song-Yu Yang; Chi-Yao Yu; Ping-Yu Chen; Tzung-Han Wu; Mohammed Hassan; Chi-Tsan Chen; Chao-Wei Wang; Yen-Chuan Huang; Li-Han Hung; Wei-Hao Chiu; Anson Lin; et al. (ISSCC, 2020)

RFIC and RF Module for 5G Applications. - Ming-Da Tsai; Song-Yu Yang; Chi-Yao Yu; Ping-Yu Chen; Tzung-Han Wu; Mohammed Hassan; Chi-Tsan Chen; Chao-Wei Wang; Yen-Chuan Huang; Li-Han Huang; Wei-Hao Chiu; Anson Lin; et al. (VLSI-DAT, 2020)