Paged cache: an efficient partition architecture for reducing power, area and access time. - Yen-Jen Chang; Feipei Lai (APCCAS (2), 2002)

Energy analysis of bipartition architecture for pipelined circuits. - Shanq-Jang Ruan; Edwin Naroska; Yen-Jen Chang; Chia-Lin Ho; Feipei Lai (APCCAS (2), 2002)

Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost. - Yen-Jen Chang; Feipei Lai; Shanq-Jang Ruan (ICCD, 2002)

An Efficient Two-Level Filter Scheme for Low Power Cache. - Yen-Jen Chang; Feipei Lai; Shanq-Jang Ruan (IWLS, 2002)

ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. - Shanq-Jang Ruan; Edwin Naroska; Yen-Jen Chang; Feipei Lai; Uwe Schwiegelshohn (IEEE Trans. Very Large Scale Integr. Syst., 2002)

A power-aware SWDR cell for reducing cache write power. - Yen-Jen Chang; Chia-Lin Yang; Feipei Lai (ISLPED, 2003)

Design and analysis of low-power cache using two-level filter scheme. - Yen-Jen Chang; Shanq-Jang Ruan; Feipei Lai (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power. - Yen-Jen Chang; Chia-Lin Yang; Feipei Lai (DATE, 2004)

Enhanced object management for high performance web proxies. - Yen-Jen Chang; Yung-Ching Weng; Feipei Lai (SAC, 2004)

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero. - Yen-Jen Chang; Feipei Lai; Chia-Lin Yang (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. - Yen-Jen Chang; Feipei Lai (IEEE Micro, 2005)

Lazy BTB: reduce BTB energy consumption using dynamic profiling. - Yen-Jen Chang (ASP-DAC, 2006)

An ultra low-power TLB design. - Yen-Jen Chang (DATE, 2006)

An Alternative Real-Time Filter Scheme to Block Buffering. - Yen-Jen Chang (VLSI Design, 2006)

An Energy-Efficient BTB Lookup Scheme for Embedded Processors. - Yen-Jen Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Improve CAM power efficiency using decoupled match line scheme. - Yen-Jen Chang; Yuan-Hong Liao; Shanq-Jang Ruan (DATE, 2007)

Two New Techniques Integrated for Energy-Efficient TLB Design. - Yen-Jen Chang; Maofeng Lan (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Exploiting frequent opcode locality for power efficient instruction cache. - Yen-Jen Chang (ACM Great Lakes Symposium on VLSI, 2008)

Hybrid-Type CAM Design for Both Power and Performance Efficiency. - Yen-Jen Chang; Yuan-Hong Liao (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Novel High Performance Ternary CAM (TCAM) for LPM. - Yung-Feng Cheng; Yen-Jen Chang (ESA, 2009)

Low Power Selected Gating Frame Buffer (SGFB) Design. - Jin-Wei Yang; Yen-Jen Chang (ESA, 2009)

A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup. - Yen-Jen Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power. - Yen-Jen Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table. - Yen-Jen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A low-power TCAM design using mask-aware match-line (MAML) technique. - Yen-Jen Chang; Tung-Chi Wu (ACM Great Lakes Symposium on VLSI, 2011)

Fast color-spatial feature based image retrieval methods. - Chuen-Horng Lin; Der-Chen Huang; Yung-Kuan Chan; Kai-Hung Chen; Yen-Jen Chang (Expert Syst. Appl., 2011)

Low-power content-addressable memory design using a double match-line (DML) architecture. - Ya-Chun Lin; Yen-Jen Chang; Tung-Chi Wu (MWSCAS, 2013)

Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating. - Yen-Jen Chang; Kun-Lin Tsai; Hsiang-Jen Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Improving the performance of port range check for network packet filtering. - Yen-Jen Chang; Hsiang-Yu Lu (ACM Trans. Design Autom. Electr. Syst., 2013)

Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism. - Kun-Lin Tsai; Yen-Jen Chang; Yu-Cheng Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Master-Slave Match Line Design for Low-Power Content-Addressable Memory. - Yen-Jen Chang; Tung-Chi Wu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Low leakage mask vertical control TCAM for network router. - Yu-Cheng Cheng; Jin-Hao Chen; Tung-Chi Wu; Yen-Jen Chang (APCCAS, 2016)

Radix-4 adder design with refined carry. - Chun-Hsiang Lai; Yu-Cheng Cheng; Tung-Chi Wu; Yen-Jen Chang (DSC, 2017)

Imprecise 4-2 compressor design used in image processing applications. - Yen-Jen Chang; Yu-Cheng Cheng; Yi-Fong Lin; Shao-Chi Liao; Chun-Hsiang Lai; Tung-Chi Wu (IET Circuits Devices Syst., 2019)

A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism. - Yen-Jen Chang; Yu-Cheng Cheng; Shao-Chi Liao; Chun-Huo Hsiao (IEEE Access, 2020)

Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment. - Yen-Jen Chang; Kun-Lin Tsai; Yu-Cheng Cheng; Meng-Rong Lu (Comput. Electr. Eng., 2020)

Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme. - Kun-Lin Tsai; Yen-Jen Chang; Chien-Ho Wang; Cheng-Tse Chiang (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Data Retention-Based Low Leakage Power TCAM for Network Packet Routing. - Yen-Jen Chang; Kun-Lin Tsai; Yu-Cheng Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Multi-Logic Sense Amplifier (MLSA) Design for In-Memory Computing. - Yen-Jen Chang; Shih-Hsiang Chen (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Target-Aware Yield Prediction (TAYP) Model Used to Improve Agriculture Crop Productivity. - Yen-Jen Chang; Ming-Hsin Lai; Chien-Ho Wang; Yu-Shun Huang; Jason Lin (IEEE Trans. Geosci. Remote. Sens., 2024)

Modified YOLO network model for metaphase cell detection in antinuclear antibody images. - Yen-Jen Chang; Yi-Da Wu; Yu-Lin Liao; Chien-Ho Wang; Yen-Ching Wu (Eng. Appl. Artif. Intell., 2024)

Content-aware malicious webpage detection using convolutional neural network. - Yen-Jen Chang; Kun-Lin Tsai; Wei-Cheng Jiang; Meng-Kun Liu (Multim. Tools Appl., 2024)

Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation. - Yen-Jen Chang; Kun-Lin Tsai; Chun Cheng; Xu-Yao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)