An area- and power-efficient half-rate clock and data recovery circuit. - Yen-Long Lee; Soon-Jyh Chang; Rong-Sing Chu; Yen-Chi Chen; Jih Ren Goh; Chung-Ming Huang (ISCAS, 2014)

A dual-edge sampling CES delay-locked loop based clock and data recovery circuits. - Jih Ren Goh; Yen-Long Lee; Soon-Jyh Chang (VLSI-DAT, 2015)

A low power duobinary voltage mode transmitter. - Ming-Hung Chien; Yen-Long Lee; Jih Ren Goh; Soon-Jyh Chang (ISLPED, 2017)

A quick jitter tolerance estimation technique for bang-bang CDRs. - Yen-Long Lee; Soon-Jyh Chang (ITC-Asia, 2017)

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits. - Yen-Long Lee; Soon-Jyh Chang; Yen-Chi Chen; Yu-Po Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs. - Yen-Long Lee; Yu-Po Cheng; Soon-Jyh Chang; Hsin-Wen Ting (IEEE Des. Test, 2018)