Behavior-level yield enhancement approach for large-scaled analog circuits. - Chin-Cheng Kuo; Yen-Lung Chen; I-Ching Tsai; Li-Yu Chan; Chien-Nan Jimmy Liu (DAC, 2010)

A fast heuristic approach for parametric yield enhancement of analog designs. - Chien-Nan Jimmy Liu; Yen-Lung Chen; Chin-Cheng Kuo; I-Ching Tsai (ACM Trans. Design Autom. Electr. Syst., 2012)

Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. - Yen-Lung Chen; Wan-Rong Wu; Guan-Ruei Lu; Chien-Nan Jimmy Liu (DATE, 2013)

LASER: layout-aware analog synthesis environment on laker. - Yu-Ching Liao; Yen-Lung Chen; Xian-Ting Cai; Chien-Nan Jimmy Liu; Tai-Chen Chen (ACM Great Lakes Symposium on VLSI, 2013)

A layout-aware automatic sizing approach for retargeting analog integrated circuits. - Yen-Lung Chen; Yi-Ching Ding; Yu-Ching Liao; Hsin-Ju Chang; Chien-Nan Jimmy Liu (VLSI-DAT, 2013)

REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. - Wei Wu; Wenyao Xu; Rahul Krishnan; Yen-Lung Chen; Lei He 001 (DAC, 2014)

Robust guidance law design for UAVs. - Yung-Yue Chen; Yen-Lung Chen; Bo-Hui Zhou (ICCA, 2014)

Simultaneous optimization for low dropout regulator and its error amplifier with process variation. - Yen-Lung Chen; Guan-Ming Chu; Ying-Chi Lien; Ching-Mao Lee; Chien-Nan Jimmy Liu (VLSI-DAT, 2014)

Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. - Yen-Lung Chen; Wan-Rong Wu; Chien-Nan Jimmy Liu; James Chien-Mo Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. - Yen-Lung Chen; Wei Wu; Chien-Nan Jimmy Liu; Lei He 001 (ASP-DAC, 2015)

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). - Wei Wu; Peng Gu; Yen-Lung Chen; Chien-Nan Liu; Sudhakar Pamarti; Chang Wu; Lei He 001 (FPGA, 2015)

Layout-aware analog synthesis environment with yield consideration. - Hsin-Ju Chang; Yen-Lung Chen; Conan Yeh; Chien-Nan Jimmy Liu (ISQED, 2015)

Wave digital filter based analog circuit emulation on FPGA. - Wei Wu; Yen-Lung Chen; Yue Ma; Chien-Nan Jimmy Liu; Jing-Yang Jou; Sudhakar Pamarti; Lei He 001 (ISCAS, 2016)

21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (ISSCC, 2020)

A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. - Po-Shao Chen; Yen-Lung Chen; Yu-Chi Lee; Zih-Sing Fu; Chia-Hsiang Yang (A-SSCC, 2021)

A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. - Yi-Chung Wu; Yen-Lung Chen; Chung-Hsuan Yang; Chao-Hsi Lee; Chao-Yang Yu; Nian-Shyang Chang; Ling-Chien Chen; Jia-Rong Chang; Chun-Pin Lin; Hung-Lieh Chen; Chi-Shi Chen; Jui-Hung Hung; et al. (IEEE J. Solid State Circuits, 2021)

A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. - Yen-Lung Chen; Bo-Yi Chang; Chia-Hsiang Yang; Tzi-Dar Chiueh (IEEE Trans. Parallel Distributed Syst., 2021)

A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. - Yen-Lung Chen; Chung-Hsuan Yang; Yi-Chung Wu; Chao-Hsi Lee; Wen-Ching Chen; Liang-Yi Lin; Nian-Shyang Chang; Chun-Pin Lin; Chi-Shi Chen; Jui-Hung Hung; Chia-Hsiang Yang (ISSCC, 2023)

An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. - Chung-Hsuan Yang; Yi-Chung Wu; Yen-Lung Chen; Chao-Hsi Lee; Jui-Hung Hung; Chia-Hsiang Yang (IEEE Trans. Biomed. Circuits Syst., 2023)

A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. - Po-Shao Chen; Yen-Lung Chen; Yu-Chi Lee; Zih-Sing Fu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2024)