17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme. - Meng-Fan Chang; Chien-Fu Chen; Ting-Hao Chang; Chi-Chang Shuai; Yen-Yao Wang 002; Hiroyuki Yamauchi (ISSCC, 2015)

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme. - Meng-Fan Chang; Chien-Fu Chen; Ting-Hao Chang; Chi-Chang Shuai; Yen-Yao Wang 002; Yi-Ju Chen; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2017)