18.3 A 1.2V 64Gb 8-channel 256GB/s HBM DRAM with peripheral-base-die architecture and small-swing technique on heavy load interface. - Jong-Chern Lee; Jihwan Kim; Kyung Whan Kim; Young Jun Ku; Dae Suk Kim; Chunseok Jeong; Tae Sik Yun; Hongjung Kim; Ho Sung Cho; Yeon Ok Kim; Jae-Hwan Kim; Jin Ho Kim; et al. (ISSCC, 2016)