A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme. - Yeonbae Chung; Byung-Gil Jeon; Kang-Deog Suh (IEEE J. Solid State Circuits, 2000)

A 0.4-μm 3.3-V 1T1C 4-Mb nonvolatile ferroelectric RAM with fixed bitline reference voltage scheme and data protection circuit. - Byung-Gil Jeon; Mun-Kyu Choi; Yoonjong Song; Seung-Kyu Oh; Yeonbae Chung; Kang-Deog Suh; Kinam Kim (IEEE J. Solid State Circuits, 2000)

Implementation of low-voltage static RAM with enhanced data stability and circuit speed. - Yeonbae Chung; Seung-Ho Song (Microelectron. J., 2009)

CMOS latch bit-cell array for low-power SRAM design. - Yeonbae Chung; Weijie Cheng (IEICE Electron. Express, 2010)

Design of logic-compatible embedded DRAM using gain memory cell. - Weijie Cheng; Jeong-Wook Cho; Yeonbae Chung (ISOCC, 2012)

Bit-area efficient embedded pseudo-SRAM utilising dual-threshold hybrid 2T gain cell. - Weijie Cheng; Yeonbae Chung (IET Circuits Devices Syst., 2014)

P-channel logic 2 T eDRAM macro with high retention bit architecture. - Sivasundar Manisankar; Yeonbae Chung (Int. J. Circuit Theory Appl., 2018)