A dual-mode NAND flash memory: 1-Gb multilevel and high-performance 512-Mb single-level modes. - Taehee Cho; Yeong-Taek Lee; Eun-Cheol Kim; Jin-Wook Lee; Sunmi Choi; Seungjae Lee 001; Dong-Hwan Kim; Wook-Ghee Han; Young-Ho Lim; Jae-Duk Lee; Jung-Dal Choi; Kang-Deog Suh (IEEE J. Solid State Circuits, 2001)

A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure. - Ki-Tae Park; Doo-Gon Kim; Soonwook Hwang; Myounggon Kang; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Soon-Moon Jung; Yeong-Taek Lee; Changhyun Kim; et al. (ISSCC, 2008)

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories. - Ki-Tae Park; Myounggon Kang; Doogon Kim; Soonwook Hwang; Byung Yong Choi; Yeong-Taek Lee; Changhyun Kim; Kinam Kim (IEEE J. Solid State Circuits, 2008)

A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure. - Ki-Tae Park; Myounggon Kang; Soonwook Hwang; Doo-Gon Kim; Hoosung Cho; Youngwook Jeong; Yong-Il Seo; Jae-hoon Jang; Hansoo Kim; Yeong-Taek Lee; Soon-Moon Jung; Changhyun Kim (IEEE J. Solid State Circuits, 2009)

A 31 ns Random Cycle VCAT-Based 4F 2 DRAM With Manufacturability and Enhanced Cell Efficiency. - Ki-Whan Song; Jinyoung Kim; Jae-Man Yoon; Sua Kim; Huijung Kim; Hyun-Woo Chung; Hyungi Kim; Kanguk Kim; Hwan-Wook Park; Hyun Chul Kang; Nam-Kyun Tak; Dukha Park; et al. (IEEE J. Solid State Circuits, 2010)

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. - Youngdon Choi; Ickhyun Song; Mu-Hui Park; Hoeju Chung; Sanghoan Chang; Beakhyoung Cho; Jinyoung Kim; Younghoon Oh; Dukmin Kwon; Jung Sunwoo; Junho Shin; Yoohwan Rho; et al. (ISSCC, 2012)