A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sang-Ho Kim; Jongwoo Lee; Joonsuk Kim (ISSCC, 2023)

A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Jisu Yook; Jihoon Lee; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)

A Fully Integrated, Low-Noise, Cost-Effective Single-Crystal-Oscillator-Based Clock Management IC in 28-nm CMOS. - Jaehong Jung; Seunghyun Oh; Joomyoung Kim; Jinhyeon Lee; Wonkang Kim; Euiyoung Park; Seungyong Bae; Seungjin Kim; Jaehoon Lee 005; Yelim Youn; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)