High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM. - Yeongkyo Seo; Kon-Woo Kwon; Xuanyao Fong; Kaushik Roy 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2016)

Spin-Transfer-Torque (STT) Devices for On-chip Memory and Their Applications to Low-standby Power Systems - Yeongkyo Seo (2016)

Fast and Disturb-Free Nonvolatile Flip-Flop Using Complementary Polarizer MTJ. - Yeongkyo Seo; Xuanyao Fong; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

High-Density SOT-MRAM Based on Shared Bitline Structure. - Yeongkyo Seo; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Dynamic-Reference Based Early Write Termination for Low Energy SOT-MRAM. - Taehwan Kim; Eunjong Yeo; Yunho Jang; Yeongkyo Seo; Jongsun Park 001 (ISCAS, 2020)

Area-optimized design of SOT-MRAM. - Yeongkyo Seo; Kon-Woo Kwon (IEICE Electron. Express, 2020)

Automation Framework for Digital Circuit Design and Verification. - Hayun Bong; Kyungseon Cho; Yeongkyo Seo (ISOCC, 2022)

Stochastic SOT Device Based SNN Architecture for On-Chip Unsupervised STDP Learning. - Yunho Jang; Gyuseong Kang; Taehwan Kim; Yeongkyo Seo; Kyung-Jin Lee; Byong-Guk Park; Jongsun Park 001 (IEEE Trans. Computers, 2022)

Design of an Area-Efficient and Error-Reduced CMOS Approximate Adder. - Novi Prihatiningrum; Jungu Kang; Chanyeong Choi; Yeongkyo Seo (ISOCC, 2024)

Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System. - Sureum Choi; Daejin Han; Chanyeong Choi; Yeongkyo Seo (IEEE Trans. Very Large Scale Integr. Syst., 2024)