An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers. - Sewook Hwang; Junyoung Song; Sang-Geun Bae; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. - Yeonho Lee 002; Yoonjae Choi; Sang-Geun Bae; Jaehun Jun; Junyoung Song; Sewook Hwang; Chulwoo Kim (ISSCC, 2017)

A 1.62-5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques. - Sewook Hwang; Junyoung Song; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface. - Yeonho Lee 002; Yoonjae Choi; Chulwoo Kim (ASP-DAC, 2018)

A Spread Spectrum Clock Generator With Nested Modulation Profile for a High-Resolution Display System. - Jaehun Jun; Sang-Geun Bae; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. - Jeongsik Yoo; Yeonho Lee 002; Yoonjae Choi; Hyunsu Park; Sanghune Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface. - Hyunsu Park; Junyoung Song; Yeonho Lee 002; Jincheol Sim; Jonghyuck Choi; Chulwoo Kim (ISSCC, 2019)

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. - Yeonho Lee 002; Yoonjae Choi; Junyoung Song; Sewook Hwang; Sang-Geun Bae; Jaehun Jun; Chulwoo Kim (IEEE J. Solid State Circuits, 2019)

A ΔΣ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth. - Sang-Geun Bae; Sewook Hwang; Junyoung Song; Yeonho Lee 002; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 1.69-pJ/b 14-Gb/s Digital Sub-Sampling CDR With Combined Adaptive Equalizer and Self-Error Corrector. - Yoonjae Choi; Sewook Hwang; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Chulwoo Kim (IEEE Access, 2021)

A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS. - Yoonjae Choi; Yeonho Lee 002; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End. - Jincheol Sim; Yeonho Lee 002; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)