A high-efficient and accurate fault model aiming at FPGA-based AES cryptographic applications. - Nan Liao; Xiaoxin Cui; Tian Wang; Kai Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

Employing the mixed FBB/RBB in the design of FinFET logic gates. - Tian Wang; Xiaoxin Cui; Kai Liao; Nan Liao; Yewen Ni; Dunshan Yu; Xiaole Cui (ASICON, 2015)

A practical cold boot attack on RSA private keys. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui; Gang Qu 001 (AsianHOST, 2017)

Design of router for spiking neural networks. - Yewen Ni; Xiaoxin Cui; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

Improving DFA on AES using all-fault ciphertexts. - Yewen Ni; Xiaoxin Cui; Tian Wang; Yuanning Fan; Qiankun Han; Kefei Liu 002; Xiaole Cui (ASICON, 2017)

An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias. - Xiaole Cui; Xiaoxin Cui; Yewen Ni; Min Miao; Yufeng Jin (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits. - Tian Wang; Xiaoxin Cui; Yewen Ni; Dunshan Yu; Xiaole Cui (IEEE Trans. Very Large Scale Integr. Syst., 2018)