A fast analytical technique for estimating the bounds of on-chip clock wire inductance. - Yi-Chang Lu; Kaustav Banerjee; Mustafa Celik; Robert W. Dutton (CICC, 2001)

Min/max On-Chip Inductance Models and Delay Metrics. - Yi-Chang Lu; Mustafa Celik; Tak Young; Lawrence T. Pileggi (DAC, 2001)

Modeling of Wave Behavior of Substrate Noise Coupling for Mixed-Signal IC Design. - Georgios Veronis; Yi-Chang Lu; Robert W. Dutton (ISQED, 2004)

Performance benefits of monolithically stacked 3D-FPGA. - Mingjie Lin; Abbas El Gamal; Yi-Chang Lu; S. Simon Wong (FPGA, 2006)

Performance Benefits of Monolithically Stacked 3-D FPGA. - Mingjie Lin; Abbas El Gamal; Yi-Chang Lu; S. Simon Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

A Built-in Technique for Measuring Substrate and Power-Supply Digital Switching Noise Using PMOS-Based Differential Sensors and a Waveform Sampler in System-on-Chip Applications. - Cosmin Iorga; Yi-Chang Lu; Robert W. Dutton (IEEE Trans. Instrum. Meas., 2007)

A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effects. - Kuen-Yu Tsai; Meng-Fu You; Yi-Chang Lu; Philip C. W. Ng (ICCAD, 2008)

An Asynchronous Circuit Design with Fast Forwarding Technique at Advanced Technology Node. - Chin-Khai Tang; Chun-Yen Lin; Yi-Chang Lu (ISQED, 2008)

Thermal modeling for 3D-ICs with integrated microchannel cooling. - Hitoshi Mizunuma; Chia-Lin Yang; Yi-Chang Lu (ICCAD, 2009)

Thermal-aware router-sharing architecture for 3D Network-on-Chip designs. - Yong-Ruei Huang; Jia-Hong Pan; Yi-Chang Lu (APCCAS, 2010)

A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects. - Kuen-Yu Tsai; Wei-Jhih Hsieh; Yuan-Ching Lu; Bo-Sen Chang; Sheng-Wei Chien; Yi-Chang Lu (ASP-DAC, 2010)

Light field based digital refocusing using a DSLR camera with a pinhole array mask. - Chih-Chieh Chen; Yi-Chang Lu; Ming-Shing Su (ICASSP, 2010)

Depth estimation of light field data from pinhole-masked DSLR cameras. - Chih-Chieh Chen; Shih-Chieh Fan Chiang; Xiao-Xuan Huang; Ming-Shing Su; Yi-Chang Lu (ICIP, 2010)

Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. - Hitoshi Mizunuma; Yi-Chang Lu; Chia-Lin Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Power distribution network modeling for 3-D ICs with TSV arrays. - Chi-Kai Shen; Yi-Chang Lu; Yih-Peng Chiou; Tai-Yu Cheng; Tzong-Lin Wu (ASP-DAC, 2013)

Test Generation of Path Delay Faults Induced by Defects in Power TSV. - Chi-Jih Shih; Shih-An Hsieh; Yi-Chang Lu; James Chien-Mo Li; Tzong-Lin Wu; Krishnendu Chakrabarty (Asian Test Symposium, 2013)

Parallel architecture and hardware implementation of pre-processor and post-processor for sequence assembly. - Yuan-Hsiang Kuo; Chun-Shen Liu; Yu-Cheng Li; Yi-Chang Lu (ICASSP, 2013)

Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. - Ping-Sheng Lin; Yi-Jung Chen; Chia-Lin Yang; Yi-Chang Lu (ISLPED, 2013)

A power-efficient asynchronous circuit style with selective input-channel restoring. - Chin-Khai Tang; Yi-Chang Lu (MWSCAS, 2013)

Light field data processor design for depth estimation using confidence-assisted disparities. - Shih-Chieh Fan Chiang; Po-Hsiang Hsu; Yi-Chang Lu (SoCC, 2013)

Architecture and circuit design of parallel processing elements for de novo sequence assembly. - Yu-Long Huang; Chun-Shen Liu; Yu-Cheng Li; Yi-Chang Lu (SoCC, 2013)

Analysis and implementation of Discrete Wavelet Transform for compressing four-dimensional light field data. - Chun-Liang Kuo; Yang-Yao Lin; Yi-Chang Lu (SoCC, 2013)

Thermal coupling aware task migration using neighboring core search for many-core systems. - Hitoshi Mizunuma; Yi-Chang Lu; Chia-Lin Yang (VLSI-DAT, 2013)

LineDiff Entropy: Lossless Layout Data Compression Scheme for Maskless Lithography Systems. - Chin-Khai Tang; Ming-Shing Su; Yi-Chang Lu (IEEE Signal Process. Lett., 2013)

Depth estimation for hand-held light field cameras under low light conditions. - Min-Hung Chen; Ching-Fan Chiang; Yi-Chang Lu (IC3D, 2014)

A pixel-based depth estimation algorithm and its hardware implementation for 4-D light field data. - Che-Wei Chang; Man-Rong Chen; Po-Hsiang Hsu; Yi-Chang Lu (ISCAS, 2014)

Testing of TSV-Induced Small Delay Faults for 3-D Integrated Circuits. - Chun-Yi Kuo; Chi-Jih Shih; Yi-Chang Lu; James Chien-Mo Li; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Power efficient special processor design for burrows-wheeler-transform-based short read sequence alignment. - Nae-Chyun Chen; Tai-Yin Chiu; Yu-Cheng Li; Yu-Chun Chien; Yi-Chang Lu (BioCAS, 2015)

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. - Yi-Jung Chen; Chia-Lin Yang; Ping-Sheng Lin; Yi-Chang Lu (RACS, 2015)

Step shift: A fast image segmentation algorithm and its hardware implementation for next-generation sequencing fluorescence data. - Xiao-Xuan Huang; Chun-Hsien Ho; Yu-Cheng Li; Nae-Chyun Chen; Yi-Chang Lu (APCCAS, 2016)

An FPGA-based quality filter for de novo sequence assembly pipeline. - Chun-Shen Liu; Nae-Chyun Chen; Yu-Cheng Li; Yi-Chang Lu (APCCAS, 2016)

Mask design for pinhole-array-based hand-held light field cameras with applications in depth estimation. - Che-Wei Chang; Min-Hung Chen; Kuan-Chang Chen; Chi-Ming Yeh; Yi-Chang Lu (APSIPA, 2016)

Queue-based segmentation algorithm for refining depth maps in light field camera applications. - Yi-Hsiang Chen; Nae-Chyun Chen; Yu-Hsiang Kao; Yu-Cheng Li; Yi-Chang Lu (GCCE, 2016)

An iterative re-weighted least squares processor design for deblurring parabolic camera images. - Yu-Hsiang Kao; Sheng-Jui Huang; Yi-Chang Lu (GCCE, 2016)

An orthogonal matching pursuit processor for sparse-representation-based light field data compression. - Yang-Ming Yeh; Chi-Ming Yeh; Ying-Yu Tseng; Yi-Chang Lu (GCCE, 2016)

Non-photorealistic rendering from real video sequences with discontinuity reduction using fast video segmentation. - Lu Xiao 006; Xiao-Xuan Huang; Yi-Chang Lu (ISOCC, 2016)

A special processor design for Nucleotide Basic Local Alignment Search Tool with a new Banded two-hit method. - Chih-Yu Chang; Yu-Cheng Li; Nae-Chyun Chen; Xiao-Xuan Huang; Yi-Chang Lu (NORCAS, 2016)

Deep Co-occurrence Feature Learning for Visual Object Recognition. - Ya-Fang Shih; Yang-Ming Yeh; Yen-Yu Lin; Ming-Fang Weng; Yi-Chang Lu; Yung-Yu Chuang (CVPR, 2017)

Adaptively Banded Smith-Waterman Algorithm for Long Reads and Its Hardware Accelerator. - Yi-Lun Liao; Yu-Cheng Li; Nae-Chyun Chen; Yi-Chang Lu (ASAP, 2018)

An FPGA-Based Liquid Association Calculator for Genome-Wide Co-Expression Analysis. - Chien-An Wang; Sheng-Jui Huang; Yu-Cheng Li; Yi-Chang Lu (DSP, 2018)

Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. - Shih-Wei Hsieh; Yao-Cheng Yang; Chi-Ming Yeh; Sheng-Jui Huang; Yi-Chang Lu (ICIP, 2018)

A Memory-Efficient FM-Index Constructor for Next-Generation Sequencing Applications on FPGAs. - Nae-Chyun Chen; Yu-Cheng Li; Yi-Chang Lu (ISCAS, 2018)

A High Dynamic Range Light Field Camera and Its Built-In Data Processor Design. - Po-Hsiang Hsu; Yang-Ming Yeh; Chi-Ming Yeh; Yi-Chang Lu (ISCAS, 2018)

A Hybrid Flow for Multiple Sequence Alignment with a BLASTn Based Pairwise Alignment Processor. - Mao-Jan Lin; Chih-Yu Chang; Yu-Cheng Li; Nae-Chyun Chen; Yi-Chang Lu (ISCAS, 2018)

Three-Dimensional Dynamic Programming Accelerator for Multiple Sequence Alignment. - Ruei-Ting Chien; Yi-Lun Liao; Chien-An Wang; Yu-Cheng Li; Yi-Chang Lu (NORCAS, 2018)

Banded Pair-HMM Algorithm for DNA Variant Calling and Its Hardware Accelerator Design. - Ming-Hung Chen; Mao-Jan Lin; Yu-Cheng Li; Yi-Chang Lu (BIBE, 2019)

Hardware Accelerator Design for Dynamic-Programming-Based Protein Sequence Alignment with Affine Gap Tracebacks. - Mao-Jan Lin; Yu-Cheng Li; Yi-Chang Lu (BioCAS, 2019)

Colorization of High-Frame-Rate Monochrome Videos Using Synchronized Low-Frame-Rate Color Data. - Ching-Fan Chiang; Yang-Ming Yeh; Chi-Yun Yang; Yi-Chang Lu (CCIW, 2019)

A Special-Purpose Processor for FFT-Based Digital Refocusing using 4-D Light Field Data. - Man-Rong Chen; Hao-Wei Liu; Yi-Hsien Lin; Yi-Chang Lu (ISCAS, 2019)

BLASTP-ACC: Parallel Architecture and Hardware Accelerator Design for BLAST-Based Protein Sequence Alignment. - Yu-Cheng Li; Yi-Chang Lu (IEEE Trans. Biomed. Circuits Syst., 2019)

Comprehensive Study of Keywords for Sequence-Based Automatic Annotation of Protein Functions. - Yu-Cheng Li; Mao-Jan Lin; Xiao-Xuan Huang; Chien-Yu Chen 001; Yi-Chang Lu (BIBE, 2020)

An Image Deblurring Processor for Chromatic Aberration Based on the Primal-Dual Algorithm with Cross-Channel Prior. - Chia-Han Huang; Yi-Chang Lu (ISCAS, 2020)

HDR Deghosting Using Motion-Registration-Free Fusion in the Luminance Gradient Domain. - Cheng-Yeh Liou; Cheng-Yen Chuang; Chia-Han Huang; Yi-Chang Lu (VCIP, 2020)

Hardware Architecture and Implementation of Clustered Tensor Approximation for Multi-Dimensional Visual Data. - Chi-Yun Yang; Yang-Ming Yeh; Yi-Chang Lu (VLSI-DAT, 2020)

A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping. - Sheng-Jui Huang; Yi-Hsien Lin; Chi-Hung Weng; Yi-Chang Lu (APCCAS, 2021)

3D-GFE: a Three-Dimensional Geometric-Feature Extractor for Point Cloud Data. - Yu-Chen Chou; Yen-Po Lin; Yang-Ming Yeh; Yi-Chang Lu (APSIPA ASC, 2021)

Attention EdgeConv For 3D Point Cloud Classification. - Yen-Po Lin; Yang-Ming Yeh; Yu-Chen Chou; Yi-Chang Lu (APSIPA ASC, 2021)

Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup. - Chun-Chang Yu; Yu Hen Hu; Yi-Chang Lu; Charlie Chung-Ping Chen (DATE, 2021)

A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. - Jing-Ping Wu; Yi-Chien Lin; Ying-Wei Wu; Shih-Wei Hsieh; Ching-Hsuan Tai; Yi-Chang Lu (ISCAS, 2021)

Using Regularity Unit As Guidance For Summarization-Based Image Resizing. - Fang-Tsung Hsiao; Yi-Hsien Lin; Yi-Chang Lu (VCIP, 2021)

A Hardware Accelerator for Long Sequence Alignment with the Bit-Vector Scoring Scheme and Divide-and-Conquer Traceback. - Chuan-Yu Chen; Shih-Hao Huang; Yi-Chang Lu (BioCAS, 2022)

A Nucleotide-Position-Based Data Format for Fast Variant Calling and Its Hardware Analyzer Design. - Hao-Wei Liu; Zhe-Wei Shen; Yang-Ming Yeh; Yi-Chang Lu (BioCAS, 2022)

CF-Net: Complementary Fusion Network for Rotation Invariant Point Cloud Completion. - Bo-Fan Chen; Yang-Ming Yeh; Yi-Chang Lu (ICASSP, 2022)

Shadow Removal Through Learning-Based Region Matching and Mapping Function Optimization. - Shih-Wei Hsieh; Chih-Hsiang Yang; Yi-Chang Lu (ICME, 2022)

An Alignment-Based Hardware Accelerator for Rapid Prediction of RNA Secondary Structures. - Shih-Shiuan Weng; Yang-Ming Yeh; Yu-Cheng Li; Yi-Chang Lu (ISCAS, 2022)

A Variation-Based Nighttime Image Dehazing Flow With a Physically Valid Illumination Estimator and a Luminance-Guided Coloring Model. - Chih-Hsiang Yang; Yi-Hsien Lin; Yi-Chang Lu (IEEE Access, 2022)

MSRCall: a multi-scale deep neural network to basecall Oxford Nanopore sequences. - Yang-Ming Yeh; Yi-Chang Lu (Bioinform., 2022)

Low-Light Enhancement Using a Plug-and-Play Retinex Model With Shrinkage Mapping for Illumination Estimation. - Yi-Hsien Lin; Yi-Chang Lu (IEEE Trans. Image Process., 2022)

A Memory-Efficient Accelerator for 128-Parallel Sequence-to-Graph Alignment in Variant-Enriched Regions. - Zhe-Wei Shen; Jheng-Syun Huang; Yi-Chang Lu (BioCAS, 2024)

Deep Plug-and-play Nighttime Non-blind Deblurring with Saturated Pixel Handling Schemes. - Hung-Yu Shu; Yi-Hsien Lin; Yi-Chang Lu (WACV, 2024)

Energy-Efficient Basecalling for ONT Long Reads on a Hybrid ASIC-GPU Platform. - Cheng-You Tsai; Hung-Yu Tseng; Po-Yen Chang; Yi-Chang Lu (ISVLSI, 2025)