A Group-Based Load Balance Scheme for Software Distributed Shared Memory Systems. - Yi-Chang Zhuang; Ce-Kuen Shieh; Tyng-Yue Liang; Jun-Qi Lee; Li-Ming Tseng (CCGRID, 2001)

Maximizing Speedup through Performance Prediction for Distributed Shared Memory Systems. - Yi-Chang Zhuang; Ce-Kuen Shieh; Tyng-Yue Liang; Chih-Hui Chou (ICDCS, 2001)

A Group-Based Load Balance Scheme for Software Distributed Shared Memory Systems. - Yi-Chang Zhuang; Tyng-Yue Liang; Ce-Kuen Shieh; Jun-Qi Lee; Laurence Tianruo Yang (J. Supercomput., 2004)

A multi-layer resource reconfiguration framework for grid computing. - Po-Cheng Chen; Jyh-Biau Chang; Tyng-Yeu Liang; Ce-Kuen Shieh; Yi-Chang Zhuang (MGC@Middleware, 2006)

Finding a suitable system scale to optimize program performance on software DSM systems. - Yi-Chang Zhuang; Jyh-Biau Chang; Tyng-Yeu Liang; Ce-Kuen Shieh; Laurence Tianruo Yang (Clust. Comput., 2006)

A Content Directory Management Method of Distributed UPnP Media Servers. - Chi-Chun Chen; Yi-Chang Zhuang; Jian-Hong Liu (PDPTA, 2008)

Spigot: Fragment-Level File Sharing and Consistency on Grids. - Po-Cheng Chen; Jyh-Biau Chang; Jia-Hao Yang; Yi-Chang Zhuang; Ce-Kuen Shieh (AINA, 2009)

Memory-Mapped File Approach for On-Demand Data Co-allocation on Grids. - Po-Cheng Chen; Jyh-Biau Chang; Yi-Chang Zhuang; Ce-Kuen Shieh; Tyng-Yeu Liang (CCGRID, 2009)

A DSM-based fragmented data sharing framework for grids. - Po-Cheng Chen; Jyh-Biau Chang; Ce-Kuen Shieh; Chia-Han Lin; Yi-Chang Zhuang (Future Gener. Comput. Syst., 2010)

Transparent on-demand co-allocation data access for grids. - Po-Cheng Chen; Jyh-Biau Chang; Yi-Sheng Lin; Ce-Kuen Shieh; Yi-Chang Zhuang (Int. J. Ad Hoc Ubiquitous Comput., 2010)

23.3 A highly integrated smartphone SoC featuring a 2.5GHz octa-core CPU with advanced high-performance and low-power techniques. - Hugh Mair; Gordon Gammie; Alice Wang; Sumanth Gururajarao; Ichiro Lin; HsinChen Chen; Wuan Kuo; Anand Rajagopalan; Wei-Zheng Ge; Rolf Lagerquist; Syed Rahman; C. J. Chung; et al. (ISSCC, 2015)

3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance. - Hugh Mair; Ericbill Wang; Alice Wang; Ping Kao; Yuwen Tsai; Sumanth Gururajarao; Rolf Lagerquist; Jin Son; Gordon Gammie; Gordon Lin; Achuta Thippana; Kent Li; et al. (ISSCC, 2017)

35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC. - Bo-Jr Huang; Eric Jia-Wei Fang; Sung S.-Y. Hsueh; Rory Huang; Angus Lin; Chi-Hsun Chiang; Yi-Hsuan Lin; Wen-Wen Hsieh; Barry Chen; Yi-Chang Zhuang; Cheng-Yuh Wu; Jia-Ming Chen; et al. (ISSCC, 2021)