A 2.3 μ W Wireless Intraocular Pressure/Temperature Monitor. - Yi-Chun Shih; Tueng Shen; Brian P. Otis (IEEE J. Solid State Circuits, 2011)

An Inductorless DC-DC Converter for Energy Harvesting With a 1.2-µW Bandgap-Referenced Output Controller. - Yi-Chun Shih; Brian P. Otis (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

An On-Chip Tunable Frequency Generator for Crystal-Less Low-Power WBAN Radio. - Yi-Chun Shih; Brian P. Otis (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. - Carlos Tokunaga; Joseph F. Ryan 002; Charles Augustine; Jaydeep P. Kulkarni; Yi-Chun Shih; Stephen T. Kim; Rinkle Jain; Keith A. Bowman; Arijit Raychowdhury; Muhammad M. Khellah; James W. Tschanz; Vivek De (ISSCC, 2014)

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (ISSCC, 2015)

Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. - Stephen T. Kim; Yi-Chun Shih; Kaushik Mazumdar; Rinkle Jain; Joseph F. Ryan 002; Carlos Tokunaga; Charles Augustine; Jaydeep P. Kulkarni; Krishnan Ravichandran; James W. Tschanz; Muhammad M. Khellah; Vivek De (IEEE J. Solid State Circuits, 2016)

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (ISSCC, 2018)

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2018)

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. - Kaiyuan Yang 001; Qing Dong 001; Zhehong Wang; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2018)

Recent Progress and Next Directions for Embedded MRAM Technology. - William J. Gallagher; Eric Chien; Tien-Wei Chiang; Jian-Cheng Huang; Meng-Chun Shih; C. Y. Wang; Christine Bair; George Lee; Yi-Chun Shih; Chia-Fu Lee; Roger Wang; Kuei-Hung Shen; et al. (VLSI Circuits, 2019)

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Mahmut E. Sinangil; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2019)

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $ mu$ A Sensing Resolution, and 17.5-nS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2019)

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. - Yu-Der Chih; Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Chieh-Pu Lo; Meng-Chun Shih; Kuei-Hung Shen; Harry Chuang; Tsung-Yung Jonathan Chang (ISSCC, 2020)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. - Chia-Fu Lee; Cheng-Han Lu; Cheng-En Lee; Haruki Mori; Hidehiro Fujiwara; Yi-Chun Shih; Tan-Li Chou; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2022)

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. - Yen-Cheng Chiu; Tung-Cheng Chang; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Chieh-Pu Lo; et al. (IEEE J. Solid State Circuits, 2022)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)