A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions. - Yi Diao; Yu-Liang Wu (CAD/Graphics, 2011)

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. - Xing Wei; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (ASP-DAC, 2012)

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. - Tak-Kei Lam; Xing Wei; Wen-Ben Jone; Yi Diao; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2014)

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. - Xing Wei; Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (VLSID, 2014)

A coupling area reduction technique applying ODC shifting. - Yi Diao; Tak-Kei Lam; Xing Wei; Yu-Liang Wu (DATE, 2015)

A universal macro block mapping scheme for arithmetic circuits. - Xing Wei; Yi Diao; Tak-Kei Lam; Yu-Liang Wu (DATE, 2015)

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). - Yi Diao; Xing Wei; Tak-Kei Lam; Yu-Liang Wu (ASP-DAC, 2016)

To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. - Xing Wei; Yi Diao; Yu-Liang Wu (ASP-DAC, 2016)