Clock domain crossing fault model and coverage metric for validation of SoC design. - Yi Feng 003; Zheng Zhou; Dong Tong 001; Xu Cheng 001 (DATE, 2007)

A 3D SoC design for H.264 application with on-chip DRAM stacking. - Tao Zhang 032; Kui Wang; Yi Feng 003; Yan Chen; Qun Li; Bing Shao; Jing Xie 006; Xiaodi Song; Lian Duan; Yuan Xie 001; Xu Cheng 001; Youn-Long Lin (3DIC, 2010)

A customized design of DRAM controller for on-chip 3D DRAM stacking. - Tao Zhang 032; Kui Wang; Yi Feng 003; Xiaodi Song; Lian Duan; Yuan Xie 001; Xu Cheng 001; Youn-Long Lin (CICC, 2010)

TERA: A FPGA-based trace-driven emulation framework for designing on-chip communication architectures. - Dan Liu; Yi Feng 003; Jingjin Zhou; Dong Tong 001; Xu Cheng 001; Keyi Wang (SoCC, 2010)

Research Progress of UniCore CPUs and PKUnity SoCs. - Xu Cheng 001; Xiaoyin Wang; Junlin Lu; Jiangfang Yi; Dong Tong 001; Xuetao Guan; Feng Liu; Xianhua Liu 001; Chun Yang; Yi Feng 003 (J. Comput. Sci. Technol., 2010)

Page policy control with memory partitioning for DRAM performance and power efficiency. - Mingli Xie; Dong Tong 001; Yi Feng 003; Kan Huang; Xu Cheng 001 (ISLPED, 2013)