Throughput optimization for latency-insensitive system with minimal queue insertion. - Juinn-Dar Huang; Yi-Hang Chen; Ya-Chien Ho (ASP-DAC, 2011)

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints. - Yi-Hang Chen; Jian-Yu Chen; Juinn-Dar Huang (DATE, 2014)

Two-staged parallel layer-aware partitioning for 3D designs. - Yi-Hang Chen; Yi-Ting Chen; Juinn-Dar Huang (VLSI-DAT, 2014)

ROBDD-based area minimization synthesis for reconfigurable single-electron transistor arrays. - Yi-Hang Chen; Yang Chen; Juinn-Dar Huang (VLSI-DAT, 2015)

Defect-aware synthesis for reconfigurable single-electron transistor arrays. - Juinn-Dar Huang; Yi-Hang Chen; Jia-Shin Lu (VLSI-SoC, 2017)