A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. - Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. - Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. - Jhe-En Lin; Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)