Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Chi-Chuan Chuang; Yi-Hsiang Lai; Jie-Hong R. Jiang (DAC, 2014)

Asynchronous QDI Circuit Synthesis from Signal Transition Protocols. - Bo-Yuan Huang 001; Yi-Hsiang Lai; Jie-Hong Roland Jiang (ICCAD, 2015)

A General Framework for Efficient Performance Analysis of Acyclic Asynchronous Pipelines. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (ICCAD, 2015)

SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit Synthesis. - Chun-Hong Shih; Yi-Hsiang Lai; Jie-Hong Roland Jiang (ICCAD, 2015)

Analytic approaches to the collapse operation and equivalence verification of threshold logic circuits. - Nian-Ze Lee; Hao-Yuan Kuo; Yi-Hsiang Lai; Jie-Hong R. Jiang (ICCAD, 2016)

Scalable Synthesis of PCHB-WCHB Hybrid Quasi-Delay Insensitive Circuits. - Yi-Hsiang Lai; Chi-Chuan Chuang; Jie-Hong R. Jiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. - Yuan Zhou; Udit Gupta; Steve Dai; Ritchie Zhao; Nitish Kumar Srivastava; Hanchen Jin; Joseph Featherston; Yi-Hsiang Lai; Gai Liu; Gustavo Angarita Velasquez; Wenping Wang; Zhiru Zhang (FPGA, 2018)

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. - Yi-Hsiang Lai; Yuze Chi; Yuwei Hu; Jie Wang 022; Cody Hao Yu; Yuan Zhou; Jason Cong; Zhiru Zhang (FPGA, 2019)

SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. - Yi-Hsiang Lai; Hongbo Rong; Size Zheng 001; Weihao Zhang; Xiuping Cui; Yunshan Jia; Jie Wang 022; Brendan Sullivan; Zhiru Zhang; Yun Liang 001; Youhui Zhang; Jason Cong; et al. (ICCAD, 2020)

Bring Your Own Codegen to Deep Learning Compiler. - Zhi Chen 030; Cody Hao Yu; Trevor Morris; Jorn Tuyls; Yi-Hsiang Lai; Jared Roesch; Elliott Delaye; Vin Sharma; Yida Wang 003 (CoRR, 2021)

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. - Yi-Hsiang Lai; Ecenur Ustun; Shaojie Xiang; Zhenman Fang; Hongbo Rong; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2021)

Accelerator design with decoupled hardware customizations: benefits and challenges: invited. - Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang 006; Louis-Noël Pouchet; Zhiru Zhang (DAC, 2022)

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. - Shaojie Xiang; Yi-Hsiang Lai; Yuan Zhou; Hongzheng Chen; Niansong Zhang; Debjit Pal; Zhiru Zhang (FPGA, 2022)

Automated Deep Learning Optimization via DSL-Based Source Code Transformation. - Ruixin Wang; Minghai Lu; Cody Hao Yu; Yi-Hsiang Lai; Tianyi Zhang 001 (ISSTA, 2024)