A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue. - Hidehiro Fujiwara; Yi-Hsin Nien; Chih-Yu Lin; Hsien-Yu Pan; Hao-Wen Hsu; Shin-Rung Wu; Yao-Yi Liu; Yen-Huei Chen; Hung-Jen Liao; Jonathan Chang (ISSCC, 2021)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme. - Hidehiro Fujiwara; Wei-Chang Zhao; Kinshuk Khare; Yi-Hsin Nien; Chih-Yu Lin; Cheng-Han Lin; Shan-Ru Liao; Kenta Torigoe; Shirleen Xia; Yuichiro Ishii; Yao-Yi Lin; Jhon-Jhy Liaw; et al. (ISSCC, 2025)