Enhancing rubber component reliability by response model. - Chung-Ho Wang; Yi Hsu (Comput. Ind. Eng., 2009)

Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. - Shen-Fu Hsiao; Jyun-Liang Chen; Yi Hsu; Xiang-Ting Huang (ICCE-TW, 2021)

Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. - Shen-Fu Hsiao; Jian-Ming Chen; Yu-Hong Chen; Hung-Ching Li; Yi Hsu (ISCAS, 2021)

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. - Chua-Chin Wang; Ralph Gerard B. Sangalang; Chien-Ping Kuo; Hsin-Che Wu; Yi Hsu; Shen-Fu Hsiao; Chia-Hung Yeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)