A fully-parallel step-by-step BCH decoder over composite field for NOR flash memories. - Yi-Hsun Chen; Chi-Heng Yang; Hsie-Chia Chang (VLSI-DAT, 2012)

An area-efficient BCH codec with echelon scheduling for NAND flash applications. - Chi-Heng Yang; Yi-Hsun Chen; Hsie-Chia Chang (ICC, 2013)

Updating Contexts: Ignorance and Concession. - Yi-Hsun Chen (TLLM, 2022)