An optimization-based low-power voltage scaling technique using multiple supply voltages. - Yi-Jong Yeh; Sy-Yen Kuo (ISCAS (5), 2001)

Converter-free multiple-voltage scaling techniques for low-powerCMOS digital design. - Yi-Jong Yeh; Sy-Yen Kuo; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

An Optimization-Based Multiple-Voltage Scaling Technique for Low-Power CMOS Digital Design. - Yi-Jong Yeh; Sy-Yen Kuo (J. Circuits Syst. Comput., 2002)

A Temporal Assertion Extension to Verilog. - Kai-Hui Chang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (ATVA, 2004)

Automatic Partitioner for Behavior Level Distributed Logic Simulation. - Kai-Hui Chang; Jeh-Yen Kang; Han-Wei Wang; Wei-Ting Tu; Yi-Jong Yeh; Sy-Yen Kuo (FORTE, 2005)