An integrated design environment of fault tolerant processors with flexible HW/SW solutions for versatile performance/cost/coverage tradeoffs. - Yi-Ju Ke; Yi-Chieh Ghen; Jng-Jer Huang (ITC-Asia, 2017)

Critical Signature Assertion and On-the-Fly Recovery for Control Flow Errors in Processors. - Ing-Jer Huang; Yi-Ju Ke; Shih-Jung Pao (MCSoC, 2022)