A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. - Wan Kim; Hyeok-Ki Hong; Yi-Ju Roh; Hyun-Wook Kang; Sun-Il Hwang; Dong-Shin Jo; Dong-Jin Chang; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. - Min-Jae Seo; Yi-Ju Roh; Dong-Jin Chang; Wan Kim; Ye-Dam Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. - Woo-Cheol Kim; Dong-Shin Jo; Yi-Ju Roh; Ye-Dam Kim; Seung-Tak Ryu (VLSI Circuits, 2019)

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. - Yi-Ju Roh; Dong-Jin Chang; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)