A New Modulo (2n+1) Multiplier for IDEA. - Yi-Jung Chen; Dyi-Rong Duh; Yunghsiang S. Han (Security and Management, 2004)

Branch Behavior Characterization for Multimedia Applications. - Chia-Lin Yang; Shun-Ying Wang; Yi-Jung Chen (Asia-Pacific Computer Systems Architecture Conference, 2006)

Cache leakage control mechanism for hard real-time systems. - Jaw-Wei Chi; Chia-Lin Yang; Yi-Jung Chen; Jian-Jia Chen (CASES, 2007)

An architectural co-synthesis algorithm for energy-aware network-on-chip design. - Wei-Hsuan Hung; Yi-Jung Chen; Chia-Lin Yang; Yen-Sheng Chang; Alan P. Su (SAC, 2007)

Improved Modulo (2n+1) Multiplier for IDEA. - Yi-Jung Chen; Dyi-Rong Duh; Yunghsiang Sam Han (J. Inf. Sci. Eng., 2007)

An architectural co-synthesis algorithm for energy-aware Network-on-Chip design. - Yi-Jung Chen; Chia-Lin Yang; Yen-Sheng Chang (J. Syst. Archit., 2009)

PM-COSYN: PE and memory co-synthesis for MPSoCs. - Yi-Jung Chen; Chia-Lin Yang; Po-Han Wang 001 (DATE, 2010)

TACLC: Timing-Aware Cache Leakage Control for Hard Real-Time Systems. - Yi-Jung Chen; Chia-Lin Yang; Jaw-Wei Chi; Jian-Jia Chen (IEEE Trans. Computers, 2011)

Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. - Yi-Jung Chen; Chia-Lin Yang; Jian-Jia Chen (ICCAD, 2012)

SECRET: Selective error correction for refresh energy reduction in DRAMs. - Chung-Hsiang Lin; De-Yu Shen; Yi-Jung Chen; Chia-Lin Yang; Cheng-Yuan Michael Wang (ICCD, 2012)

Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. - Ping-Sheng Lin; Yi-Jung Chen; Chia-Lin Yang; Yi-Chang Lu (ISLPED, 2013)

Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs. - Meng-Ling Tsai; Yi-Jung Chen; Yi-Ting Chen; Ru-Hua Chang (DATE, 2014)

Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs. - Yi-Jung Chen; Chia-Lin Yang; Ping-Sheng Lin; Yi-Chang Lu (RACS, 2015)

SECRET: A Selective Error Correction Framework for Refresh Energy Reduction in DRAMs. - Chung-Hsiang Lin; De-Yu Shen; Yi-Jung Chen; Chia-Lin Yang; Cheng-Yuan Michael Wang (ACM Trans. Archit. Code Optim., 2015)

Processors Allocation for MPSoCs With Single ISA Heterogeneous Multi-Core Architecture. - Yi-Jung Chen; Wen-Wei Chang; Chia-Yin Liu; Cheng-En Wu; Bo-Yuan Chen; Ming-Ying Tsai (IEEE Access, 2017)

Exploiting Write Heterogeneity of Morphable MLC/SLC SSDs in Datacenters with Service-Level Objectives. - Che-Wei Chang; Geng-You Chen; Yi-Jung Chen; Chia-Wei Yeh; Pei Yin Eng; Ana Cheung; Chia-Lin Yang (IEEE Trans. Computers, 2017)

Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memories. - Chia-Yin Liu; Cheng-En Wu; Yi-Jung Chen (RACS, 2018)

Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. - Chia-Yin Liu; Yi-Jung Chen; Masanori Hariyama (SAC, 2020)

PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. - Chung-Hsiang Lin; Shao-Fu Lin; Yi-Jung Chen; En-Yu Jenp; Chia-Lin Yang (ASP-DAC, 2022)

Tensor Movement Orchestration in Multi-GPU Training Systems. - Shao-Fu Lin; Yi-Jung Chen; Hsiang-Yun Cheng; Chia-Lin Yang (HPCA, 2023)

Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. - Jing-Jia Hung; Yi-Jung Chen; Hsiang-Yun Cheng; Hsu Kao; Chia-Lin Yang (DATE, 2025)

Image Recognition Based Precursor Detection System for Landslide Prevention. - Yuhei Oguro; Yihsin Ho; Jie-Ru Chen; Yi-Jung Chen (SII, 2025)