A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. - Mei-Wei Chen; Ming-Hung Chang; Pei-Chen Wu; Yi-Ping Kuo; Chun-Lin Yang; Yuan-Hua Chu; Wei Hwang (SoCC, 2013)

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. - Pei-Chen Wu; Yi-Ping Kuo; Chung-Shiang Wu; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (SoCC, 2014)

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. - Chung-Shiang Wu; Kai-Chun Lin; Yi-Ping Kuo; Po-Hung Chen; Yuan-Hua Chu; Wei Hwang (ISCAS, 2015)

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. - Yi-Ping Kuo; Po-Tsang Huang; Chung-Shiang Wu; Yu-Jie Liang; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (VLSI-DAT, 2015)