A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation. - Yu-Hung Huang; Yi-Shan Lu; Hsin-I Wu; Ren-Song Tsay (DAC, 2012)

Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus. - Chen Kang Lo; Mao Lin Li; Li-Chun Chen; Yi-Shan Lu; Ren-Song Tsay; Hsu-Yao Huang; Jen-Chieh Yeh (ACM Trans. Embed. Comput. Syst., 2013)

Parallel triangle counting and k-truss identification using graph-centric methods. - Chad Voegele; Yi-Shan Lu; Sreepathi Pai; Keshav Pingali (HPEC, 2017)

Can Parallel Programming Revolutionize EDA Tools? - Yi-Shan Lu; Keshav Pingali (Advanced Logic Synthesis, 2018)

Unlocking fine-grain parallelism for AIG rewriting. - Vinicius N. Possani; Yi-Shan Lu; Alan Mishchenko; Keshav Pingali; Renato P. Ribas; André Inácio Reis (ICCAD, 2018)

Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. - Wenmian Hua; Yi-Shan Lu; Keshav Pingali; Rajit Manohar (ASYNC, 2020)

An Open-Source EDA Flow for Asynchronous Logic. - Samira Ataei; Wenmian Hua; Yihang Yang; Rajit Manohar; Yi-Shan Lu; Jiayuan He 003; Sepideh Maleki; Keshav Pingali (IEEE Des. Test, 2021)

Collusive Stability with Relative Performance and Network Externalities. - Yi-Shan Lu; Chien-Shu Tsai; Jen-Yao Lee; Chung-Yang Lee (Games, 2024)