Area and Energy Efficient 2D Max-Pooling For Convolutional Neural Network Hardware Accelerator. - Bin Zhao; Yi Sheng Chong; Anh-Tuan Do (IECON, 2020)

An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2021)

Efficient Implementation of Activation Functions for LSTM accelerators. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (VLSI-SoC, 2021)

A Low-Cost High-Throughput Digital Design of Biorealistic Spiking Neuron. - Junran Pu; Wang Ling Goh; Vishnu P. Nambiar; Yi Sheng Chong; Anh Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

0.08mm2 128nW MFCC Engine for Ultra-low Power, Always-on Smart Sensing Applications. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2022)

Recovering Accuracy of RRAM-based CIM for Binarized Neural Network via Chip-in-the-loop Training. - Yi Sheng Chong; Wang Ling Goh; Yew Soon Ong; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2022)

Noise-Aware and Lightweight LSTM for Keyword Spotting Applications. - Yingfeng Wang; Yi Sheng Chong; Wang Ling Goh; Anh Tuan Do (ISOCC, 2022)

A 2.5 μW KWS Engine With Pruned LSTM and Embedded MFCC for IoT Applications. - Yi Sheng Chong; Wang Ling Goh; Vishnu P. Nambiar; Anh-Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing. - Qibang Zang; Wang Ling Goh; Yi Sheng Chong; Anh Tuan Do (AICAS, 2023)

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. - Bo Wang 020; Ming Ming Wong; Dongrui Li; Yi Sheng Chong; Jun Zhou 014; Weng-Fai Wong; Li-Shiuan Peh; Aarthy Mani; Mohit Upadhyay; Ananta Narayanan Balaji; Anh Tuan Do (ISCAS, 2023)

A 110nW Always-on Keyword Spotting Chip using Spiking CNN in 40nm CMOS. - Chen Shen; Junran Pu; Yi Sheng Chong; Zhongyi Zhang; Wang Ling Goh; Bin Zhao; Anh Tuan Do; Yuan Gao 011 (ISCAS, 2023)

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications. - Vishnu P. Nambiar; Yi Sheng Chong; Thilini Kaushalya Bandara; Dhananjaya Wijerathne; Zhaoying Li; Rohan Juneja; Li-Shiuan Peh; Tulika Mitra; Anh Tuan Do (HCS, 2024)

Quantum Readout Processing Accelerator with a CORDIC Core at Cryogenic Temperature. - Yi Sheng Chong; Hongyu Cao; Wang Ling Goh; Patrick Bore; Yuanzheng Paul Tan; Yung Szen Yap; Rainer Dumke; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2024)

A 420 GOPS/W CGRA with a Configurable MAC and Dynamic Truncation. - Yi Sheng Chong; Rakshith Harish; Rajesh Chandrasekhara Panicker; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2024)

3881 Gbps/W, 3005 µm AES Core with State Based Clock Gating for IoT applications. - Zhangyi Pei; Vishnu P. Nambiar; Yi Sheng Chong; Wang Ling Goh; Anh Tuan Do (ISCAS, 2024)

1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. - Dongrui Li; Ming Ming Wong; Yi Sheng Chong; Jun Zhou 014; Mohit Upadhyay; Ananta Narayanan Balaji; Aarthy Mani; Weng-Fai Wong; Li-Shiuan Peh; Anh Tuan Do; Bo Wang 020 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Qubit-State Discrimination using Neural Networks with Rapid and Energy-Efficient Compute Arrays. - Yuntian Liu; Yi Sheng Chong; Benjamin Lienhard; Minghao Fan; Wang Ling Goh; Vishnu P. Nambiar; Anh Tuan Do (ISCAS, 2025)