Yi Estelle Wang

Orcid: 0000-0003-2957-4203

Affiliations:
  • Continental Automotive Singapore
  • I2R A*STAR Singapore (former)


According to our database1, Yi Estelle Wang authored at least 28 papers between 2005 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A<sup>3</sup>GAN: Attribute-Aware Anonymization Networks for Face De-identification.
Proceedings of the MM '22: The 30th ACM International Conference on Multimedia, Lisboa, Portugal, October 10, 2022

Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2019
A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning on Physical Leakage Information.
IEEE Trans. Dependable Secur. Comput., 2019

2017
A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications.
ACM Trans. Embed. Comput. Syst., 2017

2016
Efficient differential fault analysis attacks to AES decryption for low cost sensors in IoTs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

High throughput and resource efficient AES encryption/decryption for SANs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms.
IEEE Trans. Computers, 2015

Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints.
IET Biom., 2015

2014
A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

FPGA-based high throughput XTS-AES encryption/decryption for storage area network.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

An improved ridge features extraction algorithm for distorted fingerprints matching.
J. Inf. Secur. Appl., 2013

Improved chaff point generation for vault scheme in bio-cryptosystems.
IET Biom., 2013

FPGA based unified architecture for public key and private key cryptosystems.
Frontiers Comput. Sci., 2013

A variable-latency floating-point division in association with predicted quotient and fixed remainder.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

An area-efficient shuffling scheme for AES implementation on FPGA.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FPGA based Rekeying for cryptographic key management in Storage Area Network.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

An Improved Differential Fault Analysis Attack to AES Using Reduced Searching Space.
Proceedings of the Cyberspace Safety and Security - 5th International Symposium, 2013

2011
A Unified Architecture for Supporting Operations of AES and ECC.
Proceedings of the Fourth International Symposium on Parallel Architectures, 2011

2008
High performance hardware security components
PhD thesis, 2008

A unified architecture for a public key cryptographic coprocessor.
J. Syst. Archit., 2008

2006
FPGA based DPA-resistant Unified Architecture for Signcryption.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

VMSIM: Virtual Machine Based a Full System Simulation Platform for Microprocessors' Functional Verification.
Proceedings of the Third International Conference on Information Technology: New Generations (ITNG 2006), 2006

Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

An Efficient Algorithm for DPA-resistent RSA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Efficient high radix modular multiplication for high-speed computing in re-configurable hardware [cryptographic applications].
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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