A reconfigurable MAC architecture implemented with mixed-Vt standard cell library. - Li-Rong Wang; Yi-Wei Chiu; Chia-Lin Hu; Ming-Hsien Tu; Shyh-Jye Jou; Chung-Len Lee (ISCAS, 2008)

8T single-ended sub-threshold SRAM with cross-point data-aware write operation. - Yi-Wei Chiu; Jihi-Yu Lin; Ming-Hsien Tu; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2011)

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. - Shao-Cheng Wang; Geng-Cing Lin; Yi-Wei Lin; Ming-Chien Tsai; Yi-Wei Chiu; Shyh-Jye Jou; Ching-Te Chuang; Nan-Chun Lien; Wei-Chiang Shih; Kuen-Di Lee; Jyun-Kai Chu (APCCAS, 2012)

A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2013)

A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (SoCC, 2014)

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Yuan-Hua Chu; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive. - Chi-Hao Hong; Yi-Wei Chiu; Jun-Kai Zhao; Shyh-Jye Jou; Wen-Tai Wang; Reed Lee (ISCAS, 2015)

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. - Yi-Wei Chiu; Yu-Hao Hu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISCAS, 2016)

AI Powered Multi-model Content Creation For Virtual Gallery Using Learning Machine. - Yen-Wen Chen; Yi-Wei Chiu; Yu-Sin Liu; Chih-Yu Huang; Yu-Chun Shen (UEMCON, 2023)