IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency. - Katherine Shu-Min Li; Yi-Yu Liao; Yuo-Wen Liu; Jr-Yang Huang (Asian Test Symposium, 2009)

Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs. - Katherine Shu-Min Li; Yi-Yu Liao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test. - Katherine Shu-Min Li; Yi-Yu Liao (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Andrew Yi-Ann Huang; Ji-Wei Li; Leon Li-Yang Chen; Nova Cheng-Yen Tsai; Sying-Jyan Wang; Chen-Shiun Lee; Leon Chou; Peter Yi-Yu Liao; Hsing-Chung Liang; Jwu E. Chen (DATE, 2020)

PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques. - Katherine Shu-Min Li; Peter Yi-Yu Liao; Leon Chou; Ken Chau-Cheung Cheng; Andrew Yi-Ann Huang; Sying-Jyan Wang; Gus Chang-Hung Han (ETS, 2020)

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering. - Katherine Shu-Min Li; Leon Li-Yang Chen; Ken Chau-Cheung Cheng; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Nova Cheng-Yen Tsai; Leon Chou; Gus Chang-Hung Han; Jwu E. Chen; Hsing-Chung Liang; Chun-Lung Hsu (ETS, 2021)

Integrated Scratch Marker for Wafer Defect Diagnosis. - Katherine Shu-Min Li; Leon Li-Yang Chen; Peter Yi-Yu Liao; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng (ITC-Asia, 2021)

WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques. - Peter Yi-Yu Liao; Katherine Shu-Min Li; Leon Li-Yang Chen; Sying-Jyan Wang; Andrew Yi-Ann Huang; Ken Chau-Cheung Cheng; Nova Cheng-Yen Tsai; Leon Chou (ITC, 2021)

Wafer Defect Pattern Classification with Explainable-Decision Tree Technique. - Ken Chau-Cheung Cheng; Katherine Shu-Min Li; Sying-Jyan Wang; Andrew Yi-Ann Huang; Chen-Shiun Lee; Leon Li-Yang Chen; Peter Yi-Yu Liao; Nova Cheng-Yen Tsai (ITC, 2022)