A construction of minimal delay Steiner tree using two-pole delay model. - LiYi Lin; Yi-Yu Liu; TingTing Hwang (ASP-DAC, 2001)

Binary decision diagram with minimum expected path length. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang; C. L. Liu 001 (DATE, 2001)

Crosstalk Minimization in Logic Synthesis for PLA. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang (DATE, 2004)

Crosstalk minimization in logic synthesis for PLAs. - Yi-Yu Liu; Kuo-Hua Wang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2006)

Crosstalk-Aware Domino-Logic Synthesis. - Yi-Yu Liu; TingTing Hwang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture. - Fu-Wei Chen; Yi-Yu Liu (DATE, 2008)

Performance-driven dual-rail insertion for chip-level pre-fabricated design. - Fu-Wei Chen; Yi-Yu Liu (DATE, 2009)

Buffer design and optimization for lut-based structured ASIC design styles. - Po-Yang Hsu; Shu-Ting Lee; Fu-Wei Chen; Yi-Yu Liu (ACM Great Lakes Symposium on VLSI, 2009)

Identifying Prostate Cancer-Related Networks from Microarray Data Based on Genotype-Phenotype Networks Using Markov Blanket Search. - Hsiang-Yuan Yeh; Yi-Yu Liu; Cheng-Yu Yeh; Von-Wun Soo (BIBE, 2010)

Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style. - Fu-Wei Chen; Yi-Yu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Dual-addressing memory architecture for two-dimensional memory access patterns. - Yen-Hao Chen; Yi-Yu Liu (DATE, 2013)

Memory management for dual-addressing memory architecture. - Ting-Wei Hung; Yen-Hao Chen; Yi-Yu Liu (IEICE Electron. Express, 2013)

Routability optimization for crossbar-switch structured ASIC design. - Mei-Hsiang Tsai; Po-Yang Hsu; Hung-Yi Li; Yi-Huang Hung; Yi-Yu Liu (ACM Trans. Design Autom. Electr. Syst., 2013)

Hybrid LUT and SOP Reconfigurable Architecture. - Po-Yang Hsu; Yung-Chih Chen; Yi-Yu Liu (J. Inf. Sci. Eng., 2014)

Buffer Design and Assignment for Structured ASIC. - Po-Yang Hsu; Yi-Yu Liu (J. Inf. Sci. Eng., 2014)

A novel cache-utilization based dynamic voltage frequency scaling (DVFS) mechanism for reliability enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (DATE, 2016)

A Novel Cache-Utilization-Based Dynamic Voltage-Frequency Scaling Mechanism for Reliability Enhancements. - Yen-Hao Chen; Yi-Lun Tang; Yi-Yu Liu; Allen C.-H. Wu; TingTing Hwang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. - An-Jie Shih; Shao-Yun Fang; Yi-Yu Liu (ICCAD, 2020)

TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. - Jen-Wei Hsieh; Yi-Yu Liu; Hung-Tse Lee; Tai Chang (IEEE Trans. Computers, 2021)

ILP-based Substrate Routing with Mismatched Via Dimension Consideration for Wire-bonding FBGA Package Design. - Jun-Sheng Wu; Chi-An Pan; Yi-Yu Liu (ACM Trans. Design Autom. Electr. Syst., 2023)

Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. - Yi-Sian Ciou; An-Jie Shih; Shao-Yun Fang; Yi-Yu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Overview of 2024 CAD contest at ICCAD. - Shao-Yun Fang; Yi-Yu Liu; Chung-Kuan Cheng; Tsun-Ming Tseng (ICCAD, 2024)

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration. - Cheng-Hsien Lin; Kuan-Ting Chen; Yi-Yu Liu; Allen C.-H. Wu; Tingting Hwang (ACM Trans. Design Autom. Electr. Syst., 2024)

Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. - Yi-Sian Ciou; Ying-Jie Jiang; Yi-Yu Liu; Shao-Yun Fang; Wen-Hao Liu 001 (ASP-DAC, 2025)

Wire-Bonding Finger Placement for FBGA Substrate Layout Design with Finger Orientation Consideration. - Yu-En Lin; Yi-Yu Liu (DATE, 2025)