Fault Modeling and Testing of Spiking Neural Network Chips. - Yi-Zhan Hsieh; Hsiao-Yin Tseng; I-Wei Chiu; James Chien-Mo Li (ITC-Asia, 2021)

Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. - Tsai-Chieh Chen; Chia-Cheng Pai; Yi-Zhan Hsieh; Hsiao-Yin Tseng; Chien-Mo James Li; Tsung-Te Liu; I-Wei Chiu (J. Electron. Test., 2021)