A 1 V 59 fJ/Step 15 MHz BW 74 dB SNDR continuous-time ΔΣ modulator with digital ELD compensation and multi-bit FIR feedback. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Xin Meng; Nancy Qian; Ed Liu; Phillip Elliott; Gabor C. Temes (A-SSCC, 2014)

A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (CICC, 2014)

A continuous-time ΔΣ modulator with a digital technique for excess loop delay compensation. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Xin Meng; Gabor C. Temes (ISCAS, 2014)

A noise-coupled low-distortion delta-sigma ADC with shifted loop delays. - Xin Meng; Yi Zhang 023; Tao He 001; Gabor C. Temes (MWSCAS, 2014)

Double-sampled wideband delta-sigma ADCs with shifted loop delays. - Xin Meng; Tao He 001; Yi Zhang 023; Gabor C. Temes (MWSCAS, 2014)

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. - Xin Meng; Jinzhou Cao; Tao He 001; Yi Zhang 023; Gabor C. Temes; Mitsuru Aniya; Kazuki Sobue; Koichi Hamashita (ESSCIRC, 2015)

A 16-bit 1KHz bandwidth micro-power multi-step incremental ADC for multi-channel sensor interface. - Tao He 001; Yi Zhang 023; Xin Meng; Gabor C. Temes; Chia-Hung Chen (ISCAS, 2015)

A noise-coupled time-interleaved delta-sigma modulator with shifted loop delays. - Xin Meng; Yi Zhang 023; Tao He 001; Pedram Payandehnia; Gabor C. Temes (ISCAS, 2015)

Incremental Analog-to-Digital Converters for High-Resolution Energy-Efficient Sensor Interfaces. - Chia-Hung Chen; Tao He 001; Yi Zhang 023; Gabor C. Temes (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

A Micro-Power Two-Step Incremental Analog-to-Digital Converter. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Patrick Yin Chiang; Gabor C. Temes (IEEE J. Solid State Circuits, 2015)

Low-Distortion Wideband Delta-Sigma ADCs With Shifted Loop Delays. - Xin Meng; Yi Zhang 023; Tao He 001; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Continuous-Time Delta-Sigma Modulator for Biomedical Ultrasound Beamformer Using Digital ELD Compensation and FIR Feedback. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

History, present state-of-art and future of incremental ADCs. - Chia-Hung Chen; Yi Zhang 023; Gabor C. Temes (ESSCIRC, 2016)

An incremental analog-to-digital converter with multi-step extended counting for sensor interfaces. - Chia-Hung Chen; Yi Zhang 023; Tao He 001; Gabor C. Temes (ISCAS, 2016)

A 35µW 96.8dB SNDR 1 kHz BW multi-step incremental ADC using multi-slope extended counting with a single integrator. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (VLSI Circuits, 2016)

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Kazuki Sobue; Koichi Hamashita; Gabor C. Temes (CICC, 2017)

Incremental ADC with parallel counting. - Tao He 001; Chia-Hung Chen; Yi Zhang 023; Gabor C. Temes (MWSCAS, 2017)

Pseudo-pseudo-differential circuits. - Tao He 001; Manjunath Kareppagoudr; Un-Ku Moon; Gabor C. Temes; Yi Zhang 023 (MWSCAS, 2017)

A 16 b Multi-Step Incremental Analog-to-Digital Converter With Single-Opamp Multi-Slope Extended Counting. - Yi Zhang 023; Chia-Hung Chen; Tao He 001; Gabor C. Temes (IEEE J. Solid State Circuits, 2017)

A 50MHZ-BW continuous-time ΔΣ ADC with dynamic error correction achieving 79.8dB SNDR and 95.2dB SFDR. - Tao He 001; Michael Ashburn; Stacy Ho; Yi Zhang 023; Gabor C. Temes (ISSCC, 2018)

A 13b-ENOB Noise Shaping SAR ADC with a Two-Capacitor DAC. - Lukang Shi; Yi Zhang 023; Yanchao Wang 001; Manjunath Kareppagoudr; Mahmoud Sadollahi; Gabor C. Temes (MWSCAS, 2018)

Robust Continuous-Time MASH Delta Sigma Modulator. - Yanchao Wang 001; Lukang Shi; Tao He 001; Yi Zhang 023; Chia-Hung Chen; Gabor C. Temes (MWSCAS, 2018)

Noise Filtering and Linearization of Single-Ended Sampled-Data Circuits. - Tao He 001; Manjunath Kareppagoudr; Yi Zhang 023; Emanuel Caceres; Un-Ku Moon; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)