The Performance Potential of Data Dependence Speculation & Collapsing. - Yiannakis Sazeides; Stamatis Vassiliadis; James E. Smith 001 (MICRO, 1996)

Trace Processors. - Eric Rotenberg; Quinn Jacobson; Yiannakis Sazeides; James E. Smith 001 (MICRO, 1997)

The Predictability of Data Values. - Yiannakis Sazeides; James E. Smith 001 (MICRO, 1997)

Modeling Program Predictability. - Yiannakis Sazeides; James E. Smith 001 (ISCA, 1998)

Limits of Data Value Predictability. - Yiannakis Sazeides; James E. Smith 001 (Int. J. Parallel Program., 1999)

How to compare the performance of two SMT microarchitectures. - Yiannakis Sazeides; Toni Juan (ISPASS, 2001)

Modeling Value Speculation. - Yiannakis Sazeides (HPCA, 2002)

Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. - André Seznec; Stephen Felix; Venkata Krishnan; Yiannakis Sazeides (ISCA, 2002)

Selecting long atomic traces for high coverage. - Roni Rosner; Micha Moffie; Yiannakis Sazeides; Ronny Ronen (ICS, 2003)

Instruction-Isomorphism in Program Execution. - Yiannakis Sazeides (J. Instr. Level Parallelism, 2003)

The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. - Yiannakis Sazeides; Rakesh Kumar 002; Dean M. Tullsen; Theofanis Constantinou (IEEE Comput. Archit. Lett., 2005)

Performance implications of single thread migration on a chip multi-core. - Theofanis Constantinou; Yiannakis Sazeides; Pierre Michaud; Damien Fetis; André Seznec (SIGARCH Comput. Archit. News, 2005)

A study of thread migration in temperature-constrained multicores. - Pierre Michaud; André Seznec; Damien Fetis; Yiannakis Sazeides; Theofanis Constantinou (ACM Trans. Archit. Code Optim., 2007)

CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches. - Marios Kleanthous; Yiannakis Sazeides (DATE, 2008)

The Significance of Affectors and Affectees Correlations for Branch Prediction. - Yiannakis Sazeides; Andreas Moustakas; Kypros Constantinides; Marios Kleanthous (HiPEAC, 2008)

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache misses. - Pierre Michaud; Yiannakis Sazeides; André Seznec (Conf. Computing Frontiers, 2010)

Extrinsic and Intrinsic Text Cloning. - Marios Kleanthous; Yiannakis Sazeides; Marios D. Dikaiakos (ISCA Workshops, 2010)

Performance-effective operation below Vcc-min. - Nikolas Ladas; Yiannakis Sazeides; Veerle Desmet (ISPASS, 2010)

RVC: a mechanism for time-analyzable real-time processors with faulty caches. - Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla; Yanos Sazeides; Mateo Valero (HiPEAC, 2011)

RVC-based time-predictable faulty caches for safety-critical systems. - Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla; Mateo Valero; Yanos Sazeides (IOLTS, 2011)

An analytical model for the calculation of the Expected Miss Ratio in faulty caches. - Daniel Sánchez 004; Yiannakis Sazeides; Juan L. Aragón; José M. García 001 (IOLTS, 2011)

Eliminating energy of same-content-cell-columns of on-chip SRAM arrays. - Bushra Ahsan; Lorena Ndreu; Isidoros Sideris; Yiannakis Sazeides; Sachin Idgunji; Emre Özer 001 (ISLPED, 2011)

CATCH: A mechanism for dynamically detecting cache-content-duplication in instruction caches. - Marios Kleanthous; Yiannakis Sazeides (ACM Trans. Archit. Code Optim., 2011)

Improving Branch Prediction by Considering Affectors and Affectees Correlations. - Yiannakis Sazeides; Andreas Moustakas; Kypros Constantinides; Marios Kleanthous (Trans. High Perform. Embed. Archit. Compil., 2011)

Thermal characterization of cloud workloads on a power-efficient server-on-chip. - Dragomir Milojevic; Sachin Idgunji; Djordje Jevdjic; Emre Ozer 001; Pejman Lotfi-Kamran; Andreas Panteli; Andreas Prodromou; Chrysostomos Nicopoulos; Damien Hardy; Babak Falsafi; Yiannakis Sazeides (ICCD, 2012)

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults. - Damien Hardy; Isidoros Sideris; Nikolas Ladas; Yiannakis Sazeides (MICRO, 2012)

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures. - Andreas Prodromou; Andreas Panteli; Chrysostomos Nicopoulos; Yiannakis Sazeides (MICRO, 2012)

Optimizing Data-Center TCO with Scale-Out Processors. - Boris Grot; Damien Hardy; Pejman Lotfi-Kamran; Babak Falsafi; Chrysostomos Nicopoulos; Yiannakis Sazeides (IEEE Micro, 2012)

Memory array protection: check on read or check on write? - Panagiota Nikolaou; Yiannakis Sazeides; Lorena Ndreu; Emre Özer 001; Sachin Idgunji (DATE, 2013)

An analytical framework for estimating TCO and exploring data center design space. - Damien Hardy; Marios Kleanthous; Isidoros Sideris; Ali G. Saidi; Emre Ozer 001; Yiannakis Sazeides (ISPASS, 2013)

Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. - Yiannakis Sazeides; Emre Özer 001; Danny Kershaw; Panagiota Nikolaou; Marios Kleanthous; Jaume Abella 001 (MICRO, 2013)

Modeling the impact of permanent faults in caches. - Daniel Sánchez 004; Yiannakis Sazeides; Juan M. Cebrian; José M. García 001; Juan L. Aragón (ACM Trans. Archit. Code Optim., 2013)

Characterization and analysis of a web search benchmark. - Zacharias Hadjilambrou; Marios Kleanthous; Yanos Sazeides (ISPASS, 2015)

Modeling the implications of DRAM failures and protection techniques on datacenter TCO. - Panagiota Nikolaou; Yiannakis Sazeides; Lorena Ndreu; Marios Kleanthous (MICRO, 2015)

HARPA: Solutions for dependable performance under physically induced performance variability. - Dimitrios Rodopoulos; Simone Corbetta; Giuseppe Massari; Simone Libutti; Francky Catthoor; Yiannakis Sazeides; Chrysostomos Nicopoulos; Antoni Portero; Etienne Cappe; Radim Vavrík; Vít Vondrák; Dimitrios Soudris; et al. (SAMOS, 2015)

Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. - Damien Hardy; Isabelle Puaut; Yiannakis Sazeides (DATE, 2016)

Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point. - Dimitrios Rodopoulos; Philippe Roussel; Francky Catthoor; Yiannakis Sazeides; Dimitrios Soudris (ERMAVSS@DATE, 2016)

Toward Multi-Layer Holistic Evaluation of System Designs. - Marios Kleanthous; Yiannakis Sazeides; Emre Özer 001; Chrysostomos Nicopoulos; Panagiota Nikolaou; Zacharias Hadjilambrou (IEEE Comput. Archit. Lett., 2016)

An Online and Real-Time Fault Detection and Localization Mechanism for Network-on-Chip Architectures. - Kypros Chrysanthou; Panayiotis Englezakis; Andreas Prodromou; Andreas Panteli; Chrysostomos Nicopoulos; Yiannakis Sazeides; Giorgos Dimitrakopoulos (ACM Trans. Archit. Code Optim., 2016)

HARPA: Tackling physically induced performance variability. - Nikolaos Zompakis; Michail Noltsis; Lorena Ndreu; Zacharias Hadjilambrou; Panayiotis Englezakis; Panagiota Nikolaou; Antoni Portero; Simone Libutti; Giuseppe Massari; Federico Sassi; Alessandro Bacchini; Chrysostomos Nicopoulos; et al. (DATE, 2017)

Error-Resilient Server Ecosystems for Edge and Cloud Datacenters. - Georgios Karakonstantis; Dimitrios S. Nikolopoulos; Dimitris Gizopoulos; Pedro Trancoso; Yiannakis Sazeides; Christos D. Antonopoulos; Srikumar Venugopal; Shidhartha Das (Computer, 2017)

A Methodology for Oracle Selection of Monitors and Knobs for Configuring an HPC System running a Flood Management Application. - Panagiota Nikolaou; Yiannakis Sazeides; Antoni Portero; Radim Vavrík; Vít Vondrák (CoRR, 2017)

BlackOut: Enabling fine-grained power gating of buffers in Network-on-Chip routers. - Davide Zoni; Andrea Canidio; William Fornaciari; Panayiotis Englezakis; Chrysostomos Nicopoulos; Yiannakis Sazeides (J. Parallel Distributed Comput., 2017)

An energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits. - Georgios Karakonstantis; Konstantinos Tovletoglou; Lev Mukhanov; Hans Vandierendonck; Dimitrios S. Nikolopoulos; Peter Lawthers; Panos K. Koutsovasilis; Manolis Maroudas; Christos D. Antonopoulos; Christos Kalogirou; Nikolaos Bellas; Spyros Lalis; et al. (DATE, 2018)

Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs. - Konstantinos Tovletoglou; Lev Mukhanov; Georgios Karakonstantis; Athanasios Chatzidimitriou; George Papadimitriou 001; Manolis Kaliorakis; Dimitris Gizopoulos; Zacharias Hadjilambrou; Yiannakis Sazeides; Alejandro Lampropulos; Shidhartha Das; Phong Vo (DSN Workshops, 2018)

Don't Correct the Tags in a Cache, Just Check Their Hamming Distance from the Lookup Tag. - Alex Gendler; Arkady Bramnik; Ariel Szapiro; Yiannakis Sazeides (HPCA, 2018)

To Detect or to Correct? - Arkady Bramnik; Yiannakis Sazeides (IOLTS, 2018)

Leveraging CPU Electromagnetic Emanations for Voltage Noise Characterization. - Zacharias Hadjilambrou; Shidhartha Das; Marco A. Antoniades; Yiannakis Sazeides (MICRO, 2018)

Fast Estimations of Failure Probability Over Long Time Spans. - Michail Noltsis; Panayiotis Englezakis; Eleni Maragkoudaki; Chrysostomos Nicopoulos; Dimitrios Rodopoulos; Francky Catthoor; Yiannakis Sazeides; Davide Zoni; Dimitrios Soudris (NANOARCH, 2018)

Sensing CPU Voltage Noise Through Electromagnetic Emanations. - Zacharias Hadjilambrou; Shidhartha Das; Marco A. Antoniades; Yiannakis Sazeides (IEEE Comput. Archit. Lett., 2018)

Error-Shielded Register Renaming Sub-system for a Dynamically Scheduled Out-of-Order Core. - Ron Gabor; Yiannakis Sazeides; Arkady Bramnik; Alexandros Andreou; Chrysostomos Nicopoulos; Karyofyllis Patsidis; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DATE, 2019)

GeST: An Automatic Framework For Generating CPU Stress-Tests. - Zacharias Hadjilambrou; Shidhartha Das; Paul N. Whatmough; David M. Bull; Yiannakis Sazeides (ISPASS, 2019)

Comprehensive Characterization of an Open Source Document Search Engine. - Zacharias Hadjilambrou; Marios Kleanthous; Georgia Antoniou; Antoni Portero; Yiannakis Sazeides (ACM Trans. Archit. Code Optim., 2019)

2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD). - Yiannakis Sazeides; Arkady Bramnik; Ron Gabor; Chrysostomos Nicopoulos; Ramon Canal; Dimitris Konstantinou; Giorgos Dimitrakopoulos (DFT, 2020)

Techniques for Reducing the Connected-Standby Energy Consumption of Mobile Devices. - Jawad Haj-Yahya; Yanos Sazeides; Mohammed Alser; Efraim Rotem; Onur Mutlu (HPCA, 2020)

Performance Characterization of Simultaneous Multi-Threading and Index Partitioning for an Online Document Search Application. - Georgia Antoniou; Zacharias Hadjilambrou; Yiannakis Sazeides (ISPASS, 2020)

Identification of an Entire Workload's CPU-Vmin from the n-First Seconds of its Execution Based on Performance Counters. - Panagiota Nikolaou; Yiannakis Sazeides (ISPASS, 2020)

SRAM Arrays with Built-in Parity Computation for Real-Time Error Detection in Cache Tag Arrays. - Ramon Canal; Yiannakis Sazeides; Arkady Bramnik (DATE, 2021)

I-DVFS: Instantaneous Frequency Switch During Dynamic Voltage and Frequency Scaling. - Alex Gendler; Ernest Knoll; Yiannakis Sazeides (IEEE Micro, 2021)

Harnessing CPU Electromagnetic Emanations for Resonance-Induced Voltage-Noise Characterization. - Zacharias Hadjilambrou; Shidhartha Das; Marco A. Antoniades; Yiannakis Sazeides (IEEE Trans. Computers, 2021)

INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling. - Panagiota Nikolaou; Yiannakis Sazeides; Maria K. Michael (DFT, 2022)

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors. - Jawad Haj-Yahya; Jeremie S. Kim; Abdullah Giray Yaglikçi; Jisung Park 001; Efraim Rotem; Yanos Sazeides; Onur Mutlu (HPCA, 2022)

AgilePkgC: An Agile System Idle State Architecture for Energy Proportional Datacenter Servers. - Georgia Antoniou; Haris Volos 001; Davide B. Bartolini; Tom Rollet; Yiannakis Sazeides; Jawad Haj-Yahya (MICRO, 2022)

AgileWatts: An Energy-Efficient CPU Core Idle-State Architecture for Latency-Sensitive Server Applications. - Jawad Haj-Yahya; Haris Volos 001; Davide B. Bartolini; Georgia Antoniou; Jeremie S. Kim; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Zhirui Chen; Ye Geng; Onur Mutlu; Yiannakis Sazeides (MICRO, 2022)

IDLD: Instantaneous Detection of Leakage and Duplication of Identifiers used for Register Renaming. - Yiannakis Sazeides; Alex Gerber; Ron Gabor; Arkady Bramnik; George Papadimitriou 001; Dimitris Gizopoulos; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos; Karyofyllis Patsidis (MICRO, 2022)

A Real-Time Error Detection (RTD) Architecture and Its Use for Reliability and Post-Silicon Validation for F/F Based Memory Arrays. - Yiannakis Sazeides; Arkady Bramnik; Ron Gabor; Ramon Canal (IEEE Trans. Emerg. Top. Comput., 2022)

On the Evaluation of the Total-Cost-of-Ownership Trade-Offs in Edge vs Cloud Deployments: A Wireless-Denial-of-Service Case Study. - Panagiota Nikolaou; Yiannakis Sazeides; Alejandro Lampropulos; Denis Guilhot; Andrea Bartoli; George Papadimitriou 001; Athanasios Chatzidimitriou; Dimitris Gizopoulos; Konstantinos Tovletoglou; Lev Mukhanov; Georgios Karakonstantis (IEEE Trans. Sustain. Comput., 2022)

Taming Performance Variability caused by Client-Side Hardware Configuration. - Georgia Antoniou; Haris Volos 001; Yiannakis Sazeides (IISWC, 2024)

Agile C-states: A Core C-state Architecture for Latency Critical Applications Optimizing both Transition and Cold-Start Latency. - Georgia Antoniou; Davide B. Bartolini; Haris Volos 001; Marios Kleanthous; Zhe Wang 023; Kleovoulos Kalaitzidis; Tom Rollet; Ziwei Li; Onur Mutlu; Yiannakis Sazeides; Jawad Haj-Yahya (ACM Trans. Archit. Code Optim., 2024)

Leveraging control-flow similarity to reduce branch predictor cold effects in microservices. - Haris Volos 001; Stylianos Vassiliou; Georgia Antoniou; Davide Basilio Bartolini; Yiannakis Sazeides (ISCA, 2025)

Analyzing a Two-Tier Disaggregated Memory Protection Scheme Based on Memory Replication. - Haris Volos 001; Yiannakis Sazeides (CoRR, 2025)