Efficient synthesis of AND/XOR networks. - Yibin Ye; Kaushik Roy 001 (ASP-DAC, 1997)

A Graph-Based Synthesis Algorithm for AND/XOR Networks. - Yibin Ye; Kaushik Roy 001 (DAC, 1997)

Quasi-static energy recovery logic and supply-clock generation circuits. - Yibin Ye; Kaushik Roy 001; Georgios I. Stamoulis (ISLPED, 1997)

Estimation of average switching power under accurate modeling of signal correlations. - Zhanping Chen; Kaushik Roy 001; Yibin Ye (CICC, 1998)

Power Consumption in XOR-Based Circuits. - Yibin Ye; Kaushik Roy 001; Rolf Drechsler (ASP-DAC, 1999)

Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications. - Liqiong Wei; Zhanping Chen; Kaushik Roy 001; Yibin Ye; Vivek De (DAC, 1999)

Design and optimization of dual-threshold circuits for low-voltage low-power applications. - Liqiong Wei; Zhanping Chen; Kaushik Roy 001; Mark C. Johnson; Yibin Ye; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 1999)

Dynamic noise analysis in precharge-evaluate circuits. - Dinesh Somasekhar; Seung Hoon Choi; Kaushik Roy 001; Yibin Ye; Vivek De (DAC, 2000)

QSERL: quasi-static energy recovery logic. - Yibin Ye; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2001)

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. - Tanay Karnik; Yibin Ye; James W. Tschanz; Liqiong Wei; Steven M. Burns; Venkatesh Govindarajulu; Vivek De; Shekhar Borkar (DAC, 2002)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. - Fatih Hamzaoglu; Yibin Ye; Ali Keshavarzi; Kevin Zhang 001; Siva G. Narendra; Shekhar Borkar; Mircea R. Stan; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Dynamic sleep transistor and body bias for active leakage power control of microprocessors. - James W. Tschanz; Siva G. Narendra; Yibin Ye; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

A 6-GHz 16-kB L1 cache in a 100-nm dual-VT technology using a bitline leakage reduction (BLR) technique. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Ali Farhang; Vivek De (IEEE J. Solid State Circuits, 2003)

Design optimizations for microprocessors at low temperature. - Arman Vassighi; Ali Keshavarzi; Siva G. Narendra; Gerhard Schrom; Yibin Ye; Seri Lee; Greg Chrysler; Manoj Sachdev; Vivek De (DAC, 2004)

A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. - Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail (ICCD, 2005)

Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. - Yehea I. Ismail; Muhammad M. Khellah; Maged Ghoneima; James W. Tschanz; Yibin Ye; Vivek De (ISCAS (1), 2005)

Evaluation of differential vs. single-ended sensing and asymmetric cells in 90 nm logic technology for on-chip caches. - Yibin Ye; Muhammad M. Khellah; Dinesh Somasekhar; Vivek De (ISCAS, 2006)

A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. - Muhammad M. Khellah; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Yibin Ye; James W. Tschanz; Dinesh Somasekhar; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; Kevin Zhang 001; et al. (ISSCC, 2006)

A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. - Muhammad M. Khellah; Dinesh Somasekhar; Yibin Ye; Nam-Sung Kim; Jason Howard; Gregory Ruhl; Murad Sunna; James W. Tschanz; Nitin Borkar; Fatih Hamzaoglu; Gunjan Pandya; Ali Farhang; et al. (IEEE J. Solid State Circuits, 2007)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. - Maged Ghoneima; Muhammad M. Khellah; James W. Tschanz; Yibin Ye; Nasser A. Kurd; Javed Barkatullah; Srikanth Nimmagadda; Yehea I. Ismail; Vivek K. De (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

EasyFace: a realistic face modeling and facial animation authoring system. - Yibin Ye; Mingmin Zhang; Huansen Li; Ruiying Jiang; Xing Tang 002; Zhigeng Pan (VRCAI, 2009)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

Photo Realistic 3D Cartoon Face Modeling Based on Active Shape Model. - Zhigeng Pan; Huansen Li; Mingmin Zhang; Yibin Ye; Xi Cheng; Alvin Tang; Ruigang Yang (Trans. Edutainment, 2009)

Incremental-Based Extreme Learning Machine Algorithms for Time-Variant Neural Networks. - Yibin Ye; Stefano Squartini; Francesco Piazza (ICIC (1), 2010)

A Group Selection Evolutionary Extreme Learning Machine approach for Time-Variant Neural Networks. - Yibin Ye; Stefano Squartini; Francesco Piazza (WIRN, 2010)

On-Line Extreme Learning Machine for Training Time-Varying Neural Networks. - Yibin Ye; Stefano Squartini; Francesco Piazza (ICIC (3), 2011)

ELM-Based Time-Variant Neural Networks with Incremental Number of Output Basis Functions. - Yibin Ye; Stefano Squartini; Francesco Piazza (ISNN (1), 2011)

ELM-based Algorithms for Nonstationary Volterra System Identification. - Yibin Ye; Stefano Squartini; Francesco Piazza (WIRN, 2011)

Learning Capabilities of ELM-Trained Time-Varying Neural Networks. - Stefano Squartini; Yibin Ye; Francesco Piazza (WIRN, 2013)

Online sequential extreme learning machine in nonstationary environments. - Yibin Ye; Stefano Squartini; Francesco Piazza (Neurocomputing, 2013)

An environment aware epidemic spreading model and immune strategy in complex networks. - Yang Qin 001; Xiaoxiong Zhong; Hao Jiang; Yibin Ye (Appl. Math. Comput., 2015)

Opportunistic routing with admission control in wireless ad hoc networks. - Yang Qin 001; Li Li 015; Xiaoxiong Zhong; Yuanyuan Yang 001; Yibin Ye (Comput. Commun., 2015)

QR factorization based Incremental Extreme Learning Machine with growth of hidden nodes. - Yibin Ye; Yang Qin 001 (Pattern Recognit. Lett., 2015)

Combined channel assignment and network coded opportunistic routing in cognitive radio networks. - Yang Qin 001; Xiaoxiong Zhong; Yuanyuan Yang 001; Li Li 015; Yibin Ye (Comput. Electr. Eng., 2016)

Analysis for TCP in data center networks: Outcast and Incast. - Yang Qin 001; Weihong Yang; Yibin Ye; Yao Shi (J. Netw. Comput. Appl., 2016)

A unified scheme of text localization and structured data extraction for joint OCR and data mining. - Yibin Ye; Shenggao Zhu; Jing Wang 221; Qi Du; Yezhang Yang; Dandan Tu; Lanjun Wang; Jiebo Luo 001 (IEEE BigData, 2018)

3MOS: Multi-sources, Multi-resolutions, and Multi-scenes dataset for Optical-SAR image matching. - Yibin Ye; Xichao Teng; Shuo Chen; Yijie Bian; Tao Tan; Zhang Li (CoRR, 2024)

An adaptive network fusing light detection and ranging height-sliced bird's-eye view and vision for place recognition. - Rui Zheng; Zuo Jiang; Yibin Ye; Yang Ren; Hui Zeng; Junwei Li; Zhiyuan Zhang 004 (Eng. Appl. Artif. Intell., 2024)

Fast and Robust Optical-to-SAR Remote Sensing Image Registration Using Region-Aware Phase Descriptor. - Yibin Ye; Qinwei Wang; Hong Zhao; Xichao Teng; Yijie Bian; Zhang Li (IEEE Trans. Geosci. Remote. Sens., 2024)

LiDAR odometry method based on multi-scale fusion and semantic enhancement. - Yibin Ye; Yang Ren; Yiming Fan; Yiyou Liang; Hui Zeng (Robotics Auton. Syst., 2025)

Cross transformer for LiDAR-based loop closure detection. - Rui Zheng; Yang Ren; Qi Zhou; Yibin Ye; Hui Zeng (Mach. Vis. Appl., 2025)

Exploring the best way for UAV visual localization under Low-altitude Multi-view Observation Condition: a Benchmark. - Yibin Ye; Xichao Teng; Shuo Chen; Zhang Li; Leqi Liu; Qifeng Yu; Tao Tan (CoRR, 2025)