Creating a mobile-phone based geographic surveillance system for avian influenza. - Yibo Lin; Claire Heffernan (ICTD, 2009)

Addressing Animal Health Knowledge Gaps in Southern Countries: The Creation of a 2D Animal Health Resource Room. - Yibo Lin; Claire Heffernan (Electron. J. Inf. Syst. Dev. Ctries., 2009)

The Daktari: An interactive, multi-media tool for knowledge transfer among poor livestock keepers in Kenya. - Louise Nielsen; Claire Heffernan; Yibo Lin; Jun Yu (Comput. Educ., 2010)

Pushing multiple patterning in sub-10nm: are we ready? - David Z. Pan; Lars Liebmann; Bei Yu 001; Xiaoqing Xu; Yibo Lin (DAC, 2015)

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Yibo Lin; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A novel unified dummy fill insertion framework with SQP-based optimization method. - Yudong Tao; Changhao Yan; Yibo Lin; Sheng-Guo Wang; David Z. Pan; Xuan Zeng 001 (ICCAD, 2016)

Design for manufacturability and reliability in extreme-scaling VLSI. - Bei Yu 001; Xiaoqing Xu; Subhendu Roy; Yibo Lin; Jiaojiao Ou; David Z. Pan (Sci. China Inf. Sci., 2016)

Concurrent Pin Access Optimization for Unidirectional Routing. - Xiaoqing Xu; Yibo Lin; Vinicius S. Livramento; David Z. Pan (DAC, 2017)

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. - Yibo Lin; Peter Debacker; Darko Trivkovic; Ryoung-Han Kim; Praveen Raghavan; David Z. Pan (ICCD, 2017)

Placement mitigation techniques for power grid electromigration. - Wei Ye 008; Yibo Lin; Xiaoqing Xu; Wuxi Li; Yiwei Fu; Yongsheng Sun; Canhui Zhan; David Z. Pan (ISLPED, 2017)

DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. - Jiaojiao Ou; Bei Yu 001; Xiaoqing Xu; Joydeep Mitra; Yibo Lin; David Z. Pan (ISPD, 2017)

Stitch aware detailed placement for multiple E-beam lithography. - Yibo Lin; Bei Yu 001; Yi Zou; Zhuo Li 001; Charles J. Alpert; David Z. Pan (Integr., 2017)

High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. - Yibo Lin; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. - Yibo Lin; Bei Yu 001; Biying Xu; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Redundant Local-Loop Insertion for Unidirectional Routing. - Xiaoqing Xu; Yibo Lin; Meng Li 004; Jiaojiao Ou; Brian Cline; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Layout-dependent aging mitigation for critical path timing. - Che-Lun Hsu; Shaofeng Guo; Yibo Lin; Xiaoqing Xu; Meng Li 004; Runsheng Wang; Ru Huang 001; David Z. Pan (ASP-DAC, 2018)

Learning Long Term Dependencies via Fourier Recurrent Units. - Jiong Zhang; Yibo Lin; Zhao Song 002; Inderjit S. Dhillon (ICML, 2018)

Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. - Yibo Lin; Yuki Watanabe; Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; Meng Li 004; David Z. Pan (ISPD, 2018)

Machine Learning for Yield Learning and Optimization. - Yibo Lin; Mohamed Baker Alawieh; Wei Ye 008; David Z. Pan (ITC, 2018)

OpenMPL: An Open Source Layout Decomposer. - Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (CoRR, 2018)

Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. - Yibo Lin; Bei Yu 001; Meng Li 004; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Subresolution Assist Feature Generation With Supervised Data Learning. - Xiaoqing Xu; Yibo Lin; Meng Li 004; Tetsuaki Matsunawa; Shigeki Nojima; Chikaaki Kodama; Toshiya Kotani; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. - Wuxi Li; Yibo Lin; Meng Li 004; Shounak Dhar; David Z. Pan (ACM Trans. Design Autom. Electr. Syst., 2018)

Towards a Theoretical Understanding of Hashing-Based Neural Nets. - Yibo Lin; Zhao Song 002; Lin F. Yang (AISTATS, 2019)

OpenMPL: An Open Source Layout Decomposer: Invited Paper. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (ASICON, 2019)

Semi-supervised hotspot detection with self-paced multi-task learning. - Ying Chen; Yibo Lin; Tianyang Gai; Yajuan Su; Yayi Wei; David Z. Pan (ASP-DAC, 2019)

Tackling signal electromigration with learning-based detection and multistage mitigation. - Wei Ye 008; Mohamed Baker Alawieh; Yibo Lin; David Z. Pan (ASP-DAC, 2019)

LithoROC: lithography hotspot detection with explicit ROC optimization. - Wei Ye 008; Yibo Lin; Meng Li 004; Qiang Liu 001; David Z. Pan (ASP-DAC, 2019)

GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks. - Mohamed Baker Alawieh; Yibo Lin; Zaiwei Zhang; Meng Li 004; Qixing Huang; David Z. Pan (DAC, 2019)

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. - Yibo Lin; Shounak Dhar; Wuxi Li; Haoxing Ren; Brucek Khailany; David Z. Pan (DAC, 2019)

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. - Biying Xu; Yibo Lin; Xiyuan Tang; Shaolan Li; Linxiao Shen; Nan Sun 001; David Z. Pan (DAC, 2019)

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. - Wei Ye 008; Mohamed Baker Alawieh; Yibo Lin; David Z. Pan (DAC, 2019)

Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection. - Wei Ye 008; Mohamed Baker Alawieh; Meng Li 004; Yibo Lin; David Z. Pan (DATE, 2019)

Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. - ChengYue Gong; Zixuan Jiang; Dilin Wang; Yibo Lin; Qiang Liu 001; David Z. Pan (ICCAD, 2019)

elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. - Wuxi Li; Yibo Lin; David Z. Pan (ICCAD, 2019)

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. - Biying Xu; Keren Zhu 001; Mingjie Liu; Yibo Lin; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. - Keren Zhu 001; Mingjie Liu; Yibo Lin; Biying Xu; Shaolan Li; Xiyuan Tang; Nan Sun 001; David Z. Pan (ICCAD, 2019)

Device Layer-Aware Analytical Placement for Analog Circuits. - Biying Xu; Shaolan Li; Chak-Wa Pui; Derong Liu 002; Linxiao Shen; Yibo Lin; Nan Sun 001; David Z. Pan (ISPD, 2019)

A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. - Meng Li 004; Bei Yu 001; Yibo Lin; Xiaoqing Xu; Wuxi Li; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. - Yibo Lin; Meng Li 004; Yuki Watanabe; Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

High-Definition Routing Congestion Prediction for Large-Scale FPGAs. - Mohamed Baker Alawieh; Wuxi Li; Yibo Lin; Love Singhal; Mahesh A. Iyer; David Z. Pan (ASP-DAC, 2020)

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. - Mingjie Liu; Wuxi Li; Keren Zhu 001; Biying Xu; Yibo Lin; Linxiao Shen; Xiyuan Tang; Nan Sun 001; David Z. Pan (ASP-DAC, 2020)

Adaptive Layout Decomposition with Graph Embedding Neural Networks. - Wei Li 159; Jialu Xia; Yuzhe Ma; Jialu Li; Yibo Lin; Bei Yu 001 (DAC, 2020)

ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist. - Rachel Selina Rajarathnam; Yibo Lin; Yier Jin; David Z. Pan (HOST, 2020)

DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints. - Jiaqi Gu 002; Zixuan Jiang; Yibo Lin; David Z. Pan (ICCAD, 2020)

GPU-Accelerated Static Timing Analysis. - Zizheng Guo; Tsung-Wei Huang; Yibo Lin (ICCAD, 2020)

GPU Acceleration in VLSI Back-end Design: Overview and Case Studies. - Yibo Lin (ICCAD, 2020)

TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. - Wei Ye 008; Mohamed Baker Alawieh; Yuki Watanabe; Shigeki Nojima; Yibo Lin; David Z. Pan (ISPD, 2020)

Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. - Jing Chen 032; Mohamed Baker Alawieh; Yibo Lin; Maolin Zhang; Jun Zhang 057; Yufeng Guo; David Z. Pan (IEEE Access, 2020)

Cpp-Taskflow v2: A General-purpose Parallel and Heterogeneous Task Programming System at Scale. - Tsung-Wei Huang; Dian-Lun Lin; Yibo Lin; Chun-Xun Lin (CoRR, 2020)

Semisupervised Hotspot Detection With Self-Paced Multitask Learning. - Ying Chen; Yibo Lin; Tianyang Gai; Yajuan Su; Yayi Wei; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. - Yibo Lin; Wuxi Li; Jiaqi Gu 002; Haoxing Ren; Brucek Khailany; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. - Xiaohan Gao; Chenhui Deng; Mingjie Liu; Zhiru Zhang; David Z. Pan; Yibo Lin (ASP-DAC, 2021)

Physical Synthesis for Advanced Neural Network Processors. - Zhuolun He; Peiyu Liao; Siting Liu 002; Yuzhe Ma; Yibo Lin; Bei Yu 001 (ASP-DAC, 2021)

Deep Learning for Mask Synthesis and Verification: A Survey. - Yibo Lin (ASP-DAC, 2021)

Interactive Analog Layout Editing with Instant Placement Legalization. - Xiaohan Gao; Mingjie Liu; David Z. Pan; Yibo Lin (DAC, 2021)

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. - Zizheng Guo; Tsung-Wei Huang; Yibo Lin (DAC, 2021)

GPU-accelerated Path-based Timing Analysis. - Guannan Guo; Tsung-Wei Huang; Yibo Lin; Martin D. F. Wong (DAC, 2021)

Ultrafast CPU/GPU Kernels for Density Accumulation in Placement. - Zizheng Guo; Jing Mai; Yibo Lin (DAC, 2021)

Towards AQFP-Capable Physical Design Automation. - Hongjia Li; Mengshu Sun; Tianyun Zhang; Olivia Chen; Nobuyuki Yoshikawa; Bei Yu 001; Yanzhi Wang; Yibo Lin (DATE, 2021)

Global Placement with Deep Learning-Enabled Explicit Routability Optimization. - Siting Liu 002; Qi Sun 002; Peiyu Liao; Yibo Lin; Bei Yu 001 (DATE, 2021)

Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing. - Tong Qu; Yibo Lin; Zongqing Lu 002; Yajuan Su; Yayi Wei (DATE, 2021)

HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. - Zizheng Guo; Tsung-Wei Huang; Yibo Lin (ICCAD, 2021)

GPU-accelerated Critical Path Generation with Path Constraints. - Guannan Guo; Tsung-Wei Huang; Yibo Lin; Martin D. F. Wong (ICCAD, 2021)

Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning. - Xuhua Ju; Konglin Zhu; Yibo Lin; Lin Zhang 013 (IC-NIDC, 2021)

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. - Hao Chen 059; Mingjie Liu; Biying Xu; Keren Zhu 001; Xiyuan Tang; Shaolan Li; Yibo Lin; Nan Sun 001; David Z. Pan (IEEE Des. Test, 2021)

GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. - Mohamed Baker Alawieh; Yibo Lin; Zaiwei Zhang; Meng Li 004; Qixing Huang; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. - Junzhe Cai; Changhao Yan; Yudong Tao; Yibo Lin; Sheng-Guo Wang; David Z. Pan; Xuan Zeng 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. - Tsung-Wei Huang; Yibo Lin; Chun-Xun Lin; Guannan Guo; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

OpenMPL: An Open-Source Layout Decomposer. - Wei Li 159; Yuzhe Ma; Qi Sun 002; Lu Zhang; Yibo Lin; Iris Hui-Ru Jiang; Bei Yu 001; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. - Yibo Lin; Zixuan Jiang; Jiaqi Gu 002; Wuxi Li; Shounak Dhar; Haoxing Ren; Brucek Khailany; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

FPGA-Accelerated Maze Routing Kernel for VLSI Designs. - Xun Jiang 002; Jiarui Wang; Yibo Lin; Zhongfeng Wang 001 (ASP-DAC, 2022)

Efficient Critical Paths Search Algorithm using Mergeable Heap. - Kexing Zhou; Zizheng Guo; Tsung-Wei Huang; Yibo Lin (ASP-DAC, 2022)

Differentiable-timing-driven global placement. - Zizheng Guo; Yibo Lin (DAC, 2022)

A timing engine inspired graph neural network model for pre-routing slack prediction. - Zizheng Guo; Mingjie Liu; Jiaqi Gu 002; Shuhan Zhang; David Z. Pan; Yibo Lin (DAC, 2022)

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. - Jing Mai; Yibai Meng; Zhixiong Di; Yibo Lin (DAC, 2022)

LHNN: lattice hypergraph neural network for VLSI congestion prediction. - Bowen Wang; Guibao Shen; Dong Li 016; Jianye Hao; Wulong Liu; Yu Huang 005; Hongzhong Wu; Yibo Lin; Guangyong Chen; Pheng-Ann Heng (DAC, 2022)

AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2022)

DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting. - Peiyu Liao; Siting Liu 002; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (DATE, 2022)

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler. - Siting Liu 002; Peiyu Liao; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (DATE, 2022)

Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems. - Haoyu Yang; Kit Fung; Yuxuan Zhao 001; Yibo Lin; Bei Yu 001 (DATE, 2022)

EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2022)

GPU-Accelerated Rectilinear Steiner Tree Generation. - Zizheng Guo; Feng Gu; Yibo Lin (ICCAD, 2022)

DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. - Qipan Wang; Xiaohan Gao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2022)

Concurrent CPU-GPU Task Programming using Modern C++. - Tsung-Wei Huang; Yibo Lin (IPDPS Workshops, 2022)

A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation. - Zixuan Jiang; Mingjie Liu; Zizheng Guo; Shuhan Zhang; Yibo Lin; David Z. Pan (MLCAD, 2022)

Efficient Design Rule Checking Script Generation via Key Information Extraction. - Binwu Zhu; Xinyun Zhang; Yibo Lin; Bei Yu 001; Martin D. F. Wong (MLCAD, 2022)

CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA). - Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Wei Liu 160; Runsheng Wang; Ru Huang 001 (Sci. China Inf. Sci., 2022)

Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++. - Cheng-Hsiang Chiu; Tsung-Wei Huang; Zizheng Guo; Yibo Lin (CoRR, 2022)

Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview. - Junchi Yan; Xianglong Liu 001; Ruoyu Cheng; Yibo Lin (CoRR, 2022)

A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. - Zizheng Guo; Mingwei Yang 002; Tsung-Wei Huang; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System. - Tsung-Wei Huang; Dian-Lun Lin; Yibo Lin; Chun-Xun Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Adaptive Layout Decomposition With Graph Embedding Neural Networks. - Wei Li 159; Yuzhe Ma; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing. - Yibo Lin; Tong Qu; Zongqing Lu 002; Yajuan Su; Yayi Wei (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. - Yibai Meng; Wuxi Li; Yibo Lin; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. - Martin Rapp; Hussam Amrouch; Yibo Lin; Bei Yu 001; David Z. Pan; Marilyn Wolf; Jörg Henkel (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System. - Tsung-Wei Huang; Dian-Lun Lin; Chun-Xun Lin; Yibo Lin (IEEE Trans. Parallel Distributed Syst., 2022)

OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. - Jing Mai; Jiarui Wang; Zhixiong Di; Guojie Luo; Yun Liang 001; Yibo Lin (ASICON, 2023)

MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy. - Yifan Chen; Jing Mai; Xiaohan Gao; Muhan Zhang; Yibo Lin (ASP-DAC, 2023)

A Robust FPGA Router with Concurrent Intra-CLB Rerouting. - Jiarui Wang; Jing Mai; Zhixiong Di; Yibo Lin (ASP-DAC, 2023)

General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. - Zizheng Guo; Zuodong Zhang; Xun Jiang 002; Wuxi Li; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2023)

On a Moreau Envelope Wirelength Model for Analytical Global Placement. - Peiyu Liao; Hongduo Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line. - Qipan Wang; Ping Liu; Liguo Jiang; Mingjie Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2023)

LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition. - Yu Zhang 189; Yifan Chen; Zhonglin Xie; Hong Xu 001; Zaiwen Wen; Yibo Lin; Bei Yu 001 (DAC, 2023)

Mitigating Distribution Shift for Congestion Optimization in Global Placement. - Su Zheng; Lancheng Zou; Siting Liu 002; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. - Haoyi Zhang; Xiaohan Gao; Haoyang Luo; Jiahao Song; Xiyuan Tang; Junhua Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2023)

READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. - Zuodong Zhang; Meng Li 004; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2023)

Stronger Mixed-Size Placement Backbone Considering Second-Order Information. - Yifan Chen; Zaiwen Wen; Yun Liang 001; Yibo Lin (ICCAD, 2023)

Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. - Xun Jiang 002; Zizheng Guo; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. - Zuodong Zhang; Renjie Wei; Meng Li 004; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2023)

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IJCAI, 2023)

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. - Kexing Zhou; Yun Liang 001; Yibo Lin; Runsheng Wang; Ru Huang 001 (MICRO, 2023)

Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. - Jing Mai; Jiarui Wang; Zhixiong Di; Yibo Lin (CoRR, 2023)

HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction. - Yuxiang Zhao; Zhuomin Chai; Yibo Lin; Runsheng Wang; Ru Huang 001 (CoRR, 2023)

Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. - Peiyu Liao; Yuxuan Zhao 001; Dawei Guo; Yibo Lin; Bei Yu 001 (CoRR, 2023)

Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis. - Xinfa Zhang; Zuodong Zhang; Yibo Lin; Zhigang Ji; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Interactive Analog Layout Editing With Instant Placement and Routing Legalization. - Xiaohan Gao; Haoyi Zhang; Mingjie Liu; Linxiao Shen; David Z. Pan; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Introduction to the Special Issue on Machine Learning for CAD/EDA. - Yibo Lin; Avi Ziv; Haoxing Ren (ACM Trans. Design Autom. Electr. Syst., 2023)

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. - Binwu Zhu; Xinyun Zhang; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ACM Trans. Design Autom. Electr. Syst., 2023)

DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement. - Peiyu Liao; Dawei Guo; Zizheng Guo; Siting Liu 002; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A GPU-Accelerated Framework for Path-Based Timing Analysis. - Guannan Guo; Tsung-Wei Huang; Yibo Lin; Zizheng Guo; Sushma Yellapragada; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. - Zuodong Zhang; Zizheng Guo; Yibo Lin; Meng Li 004; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies. - Zhuomin Chai; Yuxiang Zhao; Wei Liu 160; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism. - Zizheng Guo; Tsung-Wei Huang; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. - Yufan Du; Zizheng Guo; Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2024)

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. - Zichen Kong; Xiyuan Tang; Wei Shi 011; Yiheng Du; Yibo Lin; Yuan Wang 001 (DAC, 2024)

G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner. - Wan-Luan Lee; Dian-Lun Lin; Tsung-Wei Huang; Shui Jiang; Tsung-Yi Ho; Yibo Lin; Bei Yu 001 (DAC, 2024)

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. - Yuan Pu 001; Fangzhou Liu; Yu Zhang 189; Zhuolun He; Yibo Lin; Kai-Yuan Chao; Bei Yu 001 (DAC, 2024)

Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. - Jiarui Wang; Xun Jiang 002; Yibo Lin (DAC, 2024)

Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. - Chenhao Xue; Chen Zhang 001; Xun Jiang 002; Zhutianya Gao; Yibo Lin; Guangyu Sun 003 (DAC, 2024)

EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. - Haoyi Zhang; Jiahao Song; Xiaohan Gao; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DAC, 2024)

Heterogeneous Static Timing Analysis with Advanced Delay Calculator. - Zizheng Guo; Tsung-Wei Huang; Zhou Jin 001; Cheng Zhuo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2024)

SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. - Haoyi Zhang; Xiaohan Gao; Zilong Shen; Jiahao Song; Xiaoxu Cheng; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2024)

Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage. - Zixi Liu; Yibo Lin; Xiaojing Su; Xiaohuan Ling; Xin Hong; Bojie Ma; Yajuan Su; Yayi Wei (ACM Great Lakes Symposium on VLSI, 2024)

An Efficient Task-Parallel Pipeline Programming Framework. - Cheng-Hsiang Chiu; Zhicheng Xiong; Zizheng Guo; Tsung-Wei Huang; Yibo Lin (HPC Asia, 2024)

Fusion of Global Placement and Gate Sizing with Differentiable Optimization. - Yufan Du; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. - Xiaohan Gao; Haoyi Zhang; Bingyang Liu; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. - Zizheng Guo; Zuodong Zhang; Wuxi Li; Tsung-Wei Huang; Xizhe Shi; Yufan Du; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management. - Jing Mai; Zuodong Zhang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. - Qipan Wang; Xueqing Li; Tianyu Jia; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method. - Chunyuan Zhao; Zizheng Guo; Rui Wang 060; Zaiwen Wen; Yun Liang 001; Yibo Lin (ICCAD, 2024)

FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects. - Tianxiang Zhu; Qipan Wang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. - Xun Jiang 002; Zhuomin Chai; Yuxiang Zhao; Yibo Lin; Runsheng Wang; Ru Huang 001 (ICLR, 2024)

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. - Siting Liu 002; Jiaxi Jiang; Zhuolun He; Ziyi Wang 010; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ISPD, 2024)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. - Yu Zhang 189; Yuan Pu 001; Fangzhou Liu; Peiyu Liao; Kai-Yuan Chao; Keren Zhu 001; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis. - Ruifan Xu; Jin Luo; Yawen Zhang; Yibo Lin; Runsheng Wang; Ru Huang 001; Yun Liang 001 (MICRO, 2024)

A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis. - Yangfan Jiang 002; Jianfei Song; Xunzhao Yin; Xiao Dong; Songyu Sun; Yibo Lin; Zhou Jin 001; Xiaoyu Yang; Cheng Zhuo (MLCAD, 2024)

First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. - Haoran Lu; Yandong Ge; Xun Jiang 002; Jiacheng Sun; Wanyue Peng; Rui Guo; Ming Li; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (VLSI Technology and Circuits, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Post-layout simulation driven analog circuit sizing. - Xiaohan Gao; Haoyi Zhang; Siyuan Ye; Mingjie Liu; David Z. Pan; Linxiao Shen; Runsheng Wang; Yibo Lin; Ru Huang 001 (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

Analytical Heterogeneous Die-to-Die 3D Placement with Macros. - Yuxuan Zhao 001; Peiyu Liao; Siting Liu 002; Jiaxi Jiang; Yibo Lin; Bei Yu 001 (CoRR, 2024)

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (CoRR, 2024)

AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models. - Haoyi Zhang; Shizhao Sun; Yibo Lin; Runsheng Wang; Jiang Bian 002 (CoRR, 2024)

Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. - Jing Mai; Jiarui Wang; Zhixiong Di; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization. - Zhixiong Di; Runzhe Tao; Jing Mai; Lin Chen; Yibo Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. - Zhixiong Di; Runzhe Tao; Lin Chen; Qiang Wu; Yibo Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration. - Yufei Chen 007; Zizheng Guo; Runsheng Wang; Ru Huang 001; Yibo Lin; Cheng Zhuo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. - Peiyu Liao; Yuxuan Zhao 001; Dawei Guo; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PathGen: An Efficient Parallel Critical Path Generation Algorithm. - Che Chang; Boyang Zhang; Cheng-Hsiang Chiu; Dian-Lun Lin; Yi-Hua Chung; Wan-Luan Lee; Zizheng Guo; Yibo Lin; Tsung-Wei Huang (ASP-DAC, 2025)

Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells. - Kairong Guo; Xiaohan Gao; Haoyi Zhang; Runsheng Wang; Ru Huang 001; Yibo Lin (ASP-DAC, 2025)

iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis. - Boyang Zhang; Che Chang; Cheng-Hsiang Chiu; Dian-Lun Lin; Yang Sui; Chih-Chun Chang; Yi-Hua Chung; Wan-Luan Lee; Zizheng Guo; Yibo Lin; Tsung-Wei Huang (ASP-DAC, 2025)

SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. - Haikang Diao; Haoyi Zhang; Jiahao Song; Haoyang Luo; Yibo Lin; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (DATE, 2025)

A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. - Haoran Lu; Xun Jiang 002; Yanbang Chu; Ziqiao Xu; Rui Guo; Wanyue Peng; Yibo Lin; Runsheng Wang; Heng Wu 007; Ru Huang 001 (DATE, 2025)

Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. - Xizhe Shi; Zizheng Guo; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2025)

MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. - Tianxiang Zhu; Qipan Wang; Yibo Lin; Runsheng Wang; Ru Huang 001 (DATE, 2025)

LayoutCopilot: LLM-Empowered Analog Layout Design towards Enhanced Human-Machine Interaction. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (ISCAS, 2025)

LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method. - Jing Mai; Chunyuan Zhao; Zuodong Zhang; Zhixiong Di; Yibo Lin; Runsheng Wang; Ru Huang 001 (ISPD, 2025)

Fast and Accurate Cross-PVT Full-Chip Leakage Power Estimation With Multi-Task Learning. - Zhuomin Chai; Wei Liu 160; Yibo Lin; Runsheng Wang (IEEE Access, 2025)

Learning placement order for constructive floorplanning. - Weiqiang Yao; Yibo Lin; Lin Li (Integr., 2025)

Analytical Heterogeneous Die-to-Die 3-D Placement With Macros. - Yuxuan Zhao 001; Peiyu Liao; Siting Liu 002; Jiaxi Jiang; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. - Xun Jiang 002; Haoran Lu; Yuxuan Zhao 001; Jiarui Wang; Zizheng Guo; Heng Wu 007; Bei Yu 001; Sung Kyu Lim; Runsheng Wang; Ru Huang 001; Yibo Lin (CoRR, 2025)

DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators. - Chenhao Xue; Yi Ren; Jinwei Zhou; Kezhi Li; Chen Zhang 001; Yibo Lin; Lining Zhang; Qiang Xu 001; Guangyu Sun 003 (CoRR, 2025)

DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization. - Yi Ren; Chenhao Xue; Jiaxing Zhang; Chen Zhang 001; Qiang Xu 001; Yibo Lin; Lining Zhang; Guangyu Sun 003 (CoRR, 2025)

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections. - Xun Jiang 002; Jiarui Wang; Jing Mai; Zhixiong Di; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Evolution of Optimization Algorithms for Global Placement via Large Language Models. - Xufeng Yao; Jiaxi Jiang; Yuxuan Zhao 001; Peiyu Liao; Yibo Lin; Bei Yu 001 (CoRR, 2025)

Sign-Off Timing Considerations via Concurrent Routing Topology Optimization. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. - Yuxiang Zhao; Zhuomin Chai; Xun Jiang 002; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

AC-Refiner: Efficient Arithmetic Circuit Optimization Using Conditional Diffusion Models. - Chenhao Xue; Kezhi Li; Jiaxing Zhang; Yi Ren; Zhengyuan Shi; Chen Zhang 001; Yibo Lin; Lining Zhang; Qiang Xu 001; Guangyu Sun 003 (CoRR, 2025)

GAP-LA: GPU-Accelerated Performance-Driven Layer Assignment. - Chunyuan Zhao; Zizheng Guo; Zuodong Zhang; Yibo Lin (CoRR, 2025)

MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. - Chenchen Zhao; Zhengyuan Shi; Xiangyu Wen; Chengjie Liu; Yi Liu; Yunhao Zhou; Yuxiang Zhao; Hefei Feng; Yinan Zhu; Gwok-Waa Wan; Xin Cheng; Weiyu Chen; et al. (CoRR, 2025)

A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. - Zhenkun Lin; Genggeng Liu; Xing Huang 001; Yibo Lin; Jixin Zhang; Wen-Hao Liu 001; Ting-Chi Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Jiajun Qin; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)