A global interconnect optimization algorithm under accurate delay model using solution space smoothing. - Yici Cai; Yibo Wang 009; Xianlong Hong (ISCAS (1), 2005)

A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model. - Yibo Wang 009; Yici Cai; Xianlong Hong (VLSI Design, 2005)

A novel technique integrating buffer insertion into timing driven placement. - Lijuan Luo; Qiang Zhou 001; Yici Cai; Xianlong Hong; Yibo Wang 009 (ISCAS, 2006)

Performance and power aware buffered tree construction. - Yibo Wang 009; Yici Cai; Xianlong Hong (ISCAS, 2006)

Stochastic Interconnect Tree Construction Algorithm with Accurate Delay and Power Consideration. - Yibo Wang 009; Yici Cai; Xianlong Hong; Yi Zou (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Symmetry constraint based on mismatch analysis for analog layout in SOI technology. - Jiayi Liu; Sheqin Dong; Xianlong Hong; Yibo Wang 009; Ou He; Satoshi Goto (ASP-DAC, 2008)

A Low-Power Buffered Tree Construction Algorithm Aware of Supply Voltage Variation. - Yibo Wang 009; Yici Cai; Xianlong Hong (ISVLSI, 2008)