Enhancing Evaluation and Feedback in Computer Organization Labs with an Automated RISC-V Processor Verification Framework. - Yichuan Gao; Ziang Liu 015; Shanshan Li; Weidong Liu (FIE, 2023)

Profile-Guided Temporal Prefetching. - Mengming Li; Qijun Zhang; Yichuan Gao; Wenji Fang; Yao Lu 031; Yongqing Ren; Zhiyao Xie (ISCA, 2025)

Efficient Architecture for RISC-V Vector Memory Access. - Hongyi Guan; Yichuan Gao; Chenlu Miao; Haoyang Wu; Hang Zhu; Mingfeng Lin; Huayue Liang (CoRR, 2025)

Profile-Guided Temporal Prefetching. - Mengming Li; Qijun Zhang; Yichuan Gao; Wenji Fang; Yao Lu; Yongqing Ren; Zhiyao Xie (CoRR, 2025)