A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. - Chi-Hsiang Huang 001; Xun Sun; Yidong Chen 005; Rajesh Pamula 001; Arindam Mandal; Visvesh Sathe 001 (ISSCC, 2021)

Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. - Chi-Hsiang Huang 001; Yidong Chen 005; Xun Sun; Arindam Mandal; Venkata Rajesh Pamula 001; Nasser A. Kurd; Visvesh S. Sathe 001 (IEEE J. Solid State Circuits, 2022)