Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. - Yifan YangGong; Sebastian Turullols; Daniel Woo; Changku Huang; King C. Yen; Venkatram Krishnaswamy; Kalon Holdbrook; Jinuk Luke Shin (A-SSCC, 2014)

4.3 Fine-grained adaptive power management of the SPARC M7 processor. - Venkatram Krishnaswamy; Jeffrey Brooks; Georgios K. Konstadinidis; Curtis McAllister; Ha Pham; Sebastian Turullols; Jinuk Luke Shin; Yifan YangGong; Haowei Zhang (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)

Maybe Only 0.5% Data is Needed: A Preliminary Exploration of Low Training Data Instruction Tuning. - Hao Chen 102; Yiming Zhang 023; Qi Zhang 077; Hantao Yang; Xiaomeng Hu; Xuetao Ma 002; Yifan Yanggong; Junbo Zhao 002 (CoRR, 2023)

Assessing Hidden Risks of LLMs: An Empirical Study on Robustness, Consistency, and Credibility. - Wentao Ye; Mingfeng Ou; Tianyi Li; Yipeng Chen; Xuetao Ma 002; Yifan Yanggong; Sai Wu; Jie Fu; Gang Chen 001; Haobo Wang 001; Junbo Zhao 002 (CoRR, 2023)

Mastering the Game of Guandan with Deep Reinforcement Learning and Behavior Regulating. - Yifan Yanggong; Hao Pan; Lei Wang (CoRR, 2024)