An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash. - Yigi Kwon; Byounghan Min; Jinhwan Lee; Wooyol Lee; Sunghyun Yang (ISCAS, 2021)

A 50 MS/s 65 dB-SNDR Pipelined SAR ADC using Capacitively Degenerated Two-Stage Dynamic Amplifier. - Hyunchul Yoon; Teawoong Kim; Yigi Kwon; Youngcheol Chae (VLSI Technology and Circuits, 2022)

An 11bit 360MS/s Pipelined SAR ADC with Dynamic Negative-C Assisted Residue Amplifier. - Yigi Kwon; Sangwoo Lee; Changuk Lee; Hyunchul Yoon; Byounghan Min; Youngcheol Chae (A-SSCC, 2023)

A 65-dB-SNDR Pipelined SAR ADC Using PVT-Robust Capacitively Degenerated Dynamic Amplifier. - Hyunchul Yoon; Changuk Lee; Taewoong Kim; Yigi Kwon; Youngcheol Chae (IEEE J. Solid State Circuits, 2023)

A 10-Bit 500-MS/s Pipelined SAR ADC With Feedback Factor Compensation in 6-nm FinFET. - Yigi Kwon; Jongyoon Won; Byounghan Min; Dooyeoun Kim; Jihyun Kim; Jeong-Hyu Yang; Youngcheol Chae (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

An 11-bit 360-MS/s Pipelined SAR ADC With Feedback Factor Compensation Using a Dynamic Negative-C-Assisted Residue Amplifier. - Yigi Kwon; Jongyoon Won; Youngcheol Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR. - Wonseon Lee; Hyeonho Han; Yigi Kwon; Seokho Yoon; Junghyun Yoon; Sanghoon Lee 009; Moon Hyung Jang; Youngcheol Chae (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)