A graph-partitioning-based approach for multi-layer constrained via minimization. - Yih-Chih Chou; Youn-Long Lin (ICCAD, 1998)

Integrating logic retiming and register placement. - Tzu-Chieh Tien; Hsiao-Pin Su; Yu-Wen Tsay; Yih-Chih Chou; Youn-Long Lin (ICCAD, 1998)

A 3-step approach for performance-driven whole-chip routing. - Yih-Chih Chou; Youn-Long Lin (ASP-DAC, 2001)

A performance-driven standard-cell placer based on a modified force-directed algorithm. - Yih-Chih Chou; Youn-Long Lin (ISPD, 2001)

Effective enforcement of path-delay constraints inperformance-driven placement. - Yih-Chih Chou; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Top-level activity-driven clock tree synthesis with clock skew variation considered. - Te-Jui Wang; Shih-Hsu Huang; Wei-Kai Cheng; Yih-Chih Chou (ISCAS, 2016)

Clocking for HPC Design: Challenges and Experience Sharing. - Yih-Chih Chou; Chien-Cheng Wu; Cheng-Hong Tsai (VLSI-DAT, 2019)

Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning Guidance. - Xuan-Xue Huang; Hsien-Chia Chen; Sheng-Wei Wang; Iris Hui-Ru Jiang; Yih-Chih Chou; Cheng-Hong Tsai (ICCAD, 2020)

Transforming Global Routing Report into DRC Violation Map with Convolutional Neural Network. - Wei-Tse Hung; Jun-Yang Huang; Yih-Chih Chou; Cheng-Hong Tsai; Mango Chia-Tso Chao (ISPD, 2020)