Logic and Fault Simulation by Cellular Automata. - Yih-Lang Li; Cheng-Wen Wu (EDAC-ETC-EUROASIC, 1994)

Cellular automata for efficient parallel logic and fault simulation. - Yih-Lang Li; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow. - Jin-Yih Li; Yih-Lang Li (ISPD, 2005)

A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation. - Yiming Li 005; Shao-Ming Yu; Yih-Lang Li (International Conference on Computational Science (4), 2007)

NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation. - Yih-Lang Li; Hsin-Yu Chen; Chih-Ta Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow. - Yih-Lang Li; Jin-Yih Li; Wen-Bin Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction. - Yu-Ning Chang; Yih-Lang Li; Wei-Tin Lin; Wen-Nai Cheng (ISPD, 2008)

Parallel solution of large-scale eigenvalue problem for master equation in protein folding dynamics. - Yiming Li 005; Shao-Ming Yu; Yih-Lang Li (J. Parallel Distributed Comput., 2008)

Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique. - Yiming Li 005; Yih-Lang Li; Shao-Ming Yu (Math. Comput. Simul., 2008)

Electronic design automation using a unified optimization framework. - Yiming Li 005; Shao-Ming Yu; Yih-Lang Li (Math. Comput. Simul., 2008)

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. - Ke-Ren Dai; Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2009)

GRPlacer: Improving routability and wire-length of global routing with circuit replacement. - Ke-Ren Dai; Chien-Hung Lu; Yih-Lang Li (ICCAD, 2009)

Topology-driven cell layout migration with collinear constraints. - De-Shiun Fu; Ying-Zhih Chaung; Yen-Hung Lin; Yih-Lang Li (ICCD, 2009)

Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization. - Yen-Hung Lin; Shu-Hsin Chang; Yih-Lang Li (ISPD, 2009)

Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing. - Peng-Yang Hung; Ying-Shu Lou; Yih-Lang Li (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Dead via minimization by simultaneous routing and redundant via insertion. - Chih-Ta Lin; Yen-Hung Lin; Guan-Chan Su; Yih-Lang Li (ASP-DAC, 2010)

Minimizing clock latency range in robust clock tree synthesis. - Wen-Hao Liu 001; Yih-Lang Li; Hui-Chi Chen (ASP-DAC, 2010)

Double patterning lithography aware gridless detailed routing with innovative conflict graph. - Yen-Hung Lin; Yih-Lang Li (DAC, 2010)

Multi-threaded collision-aware global routing with bounded-length maze routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (DAC, 2010)

Negotiation-based layer assignment for via count and via overflow minimization. - Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2011)

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. - Yen-Hung Lin; Yongchan Ban; David Z. Pan; Yih-Lang Li (ICCAD, 2011)

High-quality global routing for multiple dynamic supply voltage designs. - Wen-Hao Liu 001; Yih-Lang Li; Kai-Yuan Chao (ICCAD, 2011)

Gridless wire ordering, sizing and spacing with critical area minimization. - Yu-Wei Lee; Yen-Hung Lin; Yih-Lang Li (ISQED, 2011)

Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization. - Yen-Hung Lin; Shu-Hsin Chang; Yih-Lang Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment. - Yih-Lang Li; Yu-Ning Chang; Wen-Nai Cheng (ACM Trans. Design Autom. Electr. Syst., 2011)

Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. - Yen-Hung Lin; Yun-Jian Lo; Hian-Syun Tong; Wen-Hao Liu 001; Yih-Lang Li (ASP-DAC, 2012)

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. - Iris Hui-Ru Jiang; Zhuo Li 001; Yih-Lang Li (ICCAD, 2012)

TRIAD: A triple patterning lithography aware detailed router. - Yen-Hung Lin; Bei Yu 001; David Z. Pan; Yih-Lang Li (ICCAD, 2012)

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. - Wen-Hao Liu 001; Yih-Lang Li; Cheng-Kok Koh (ICCAD, 2012)

Optimizing the antenna area and separators in layer assignment of multi-layer global routing. - Wen-Hao Liu 001; Yih-Lang Li (ISPD, 2012)

NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. - Ke-Ren Dai; Wen-Hao Liu 001; Yih-Lang Li (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Optimization of placement solutions for routability. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (DAC, 2013)

Routing congestion estimation with real design constraints. - Wen-Hao Liu 001; Yaoguang Wei; Cliff C. N. Sze; Charles J. Alpert; Zhuo Li 001; Yih-Lang Li; Natarajan Viswanathan (DAC, 2013)

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. - Wen-Hao Liu 001; Cheng-Kok Koh; Yih-Lang Li (ISPD, 2013)

NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. - Wen-Hao Liu 001; Wei-Chun Kao; Yih-Lang Li; Kai-Yuan Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Density-aware Detailed Placement with Instant Legalization. - Sergiy Popovych; Hung-Hao Lai; Chieh-Min Wang; Yih-Lang Li; Wen-Hao Liu 001; Ting-Chi Wang (DAC, 2014)

Skillfully diminishing antenna effect in layer assignment stage. - Chih-Chien Lin; Wen-Hao Liu 001; Yih-Lang Li (VLSI-DAT, 2014)

Minimizing Critical Area on Gridless Wire Ordering, Sizing and Spacing. - Yu-Wei Lee; Yen-Hung Lin; Yih-Lang Li (J. Inf. Sci. Eng., 2014)

Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing. - Wen-Hao Liu; Yih-Lang Li (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding. - Hong-Yan Su; Chih-Hao Hsu; Yih-Lang Li (DATE, 2015)

A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding. - Hong-Yan Su; Chieh-Chu Chen; Yih-Lang Li; An-Chun Tu; Chuh-Jen Wu; Chen-Ming Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Multiple-patterning lithography-aware routing for standard cell layout synthesis. - Kuen-Wey Lin; Yih-Lang Li; Rung-Bin Lin (APCCAS, 2016)

OpenDesign flow database: the infrastructure for VLSI design and design automation research. - Jinwook Jung; Iris Hui-Ru Jiang; Gi-Joon Nam; Victor N. Kravets; Laleh Behjat; Yih-Lang Li (ICCAD, 2016)

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Great Lakes Symposium on VLSI, 2017)

DATC RDF: Robust design flow database: Invited paper. - Jinwook Jung; Pei-Yu Lee; Yan-Shiun Wu; Nima Karimpour Darav; Iris Hui-Ru Jiang; Victor N. Kravets; Laleh Behjat; Yih-Lang Li; Gi-Joon Nam (ICCAD, 2017)

Near-future traffic evaluation based navigation for automated driving vehicles. - Kuen-Wey Lin; Yih-Lang Li; Masanori Hashimoto (Intelligent Vehicles Symposium, 2017)

Pin accessibility evaluating model for improving routability of VLSI designs. - Hong-Yan Su; Shinichi Nishizawa; Yan-Shiun Wu; Jun Shiomi; Yih-Lang Li; Hidetoshi Onodera (SoCC, 2017)

LESAR: A dynamic line-end spacing aware detailed router. - Ying-Chi Wei; Radhamanjari Samanta; Yih-Lang Li (DATE, 2018)

DATC RDF: an academic flow from logic synthesis to detailed routing. - Jinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam (ICCAD, 2018)

Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties. - Kuen-Wey Lin; Masanori Hashimoto; Yih-Lang Li (ISQED, 2018)

MapReduce-based pattern classification for design space analysis. - Yan-Shiun Wu; Hong-Yan Su; Yi-Hsiang Chang; Rasit Onur Topaloglu; Yih-Lang Li (VLSI-DAT, 2018)

DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing. - Jinwook Jung; Iris Hui-Ru Jiang; Jianli Chen; Shih-Ting Lin; Yih-Lang Li; Victor N. Kravets; Gi-Joon Nam (CoRR, 2018)

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Kuen-Wey Lin; Yeh-Sheng Lin; Yih-Lang Li; Rung-Bin Lin (ACM Trans. Design Autom. Electr. Syst., 2018)

Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits. - Hsueh-Ling Yu; Yih-Lang Li; Tzu-Yi Liao; Tianchen Wang; Shu-Fei Tsai; Yiyu Shi 001 (IEEE Trans. Very Large Scale Integr. Syst., 2018)

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (DAC, 2019)

DATC RDF-2019: Towards a Complete Academic Reference Design Flow. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Victor N. Kravets; Yih-Lang Li; Shih-Ting Lin; Mingyu Woo (ICCAD, 2019)

Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. - Tai-Cheng Lee; Yih-Lang Li (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Smart Self-Checkout Carts Based on Deep Learning for Shopping Activity Recognition. - Hong-Chuan Chi; Muhammad Atif Sarwar; Yousef-Awwad Daraghmi; Kuan-Wen Liu; Tsì-Uí Ik; Yih-Lang Li (APNOMS, 2020)

DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Victor N. Kravets; Yih-Lang Li; Shih-Ting Lin; Mingyu Woo (ICCAD, 2020)

/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. - Tai-Cheng Lee; Cheng-Yen Yang; Yih-Lang Li (ICCAD, 2020)

MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hidetoshi Onodera (ICCAD, 2020)

Smart Shopping Carts Based on Mobile Computing and Deep Learning Cloud Services. - Muhammad Atif Sarwar; Yousef-Awwad Daraghmi; Kuan-Wen Liu; Hong-Chuan Chi; Tsì-Uí Ik; Yih-Lang Li (WCNC, 2020)

A Complete PCB Routing Methodology with Concurrent Hierarchical Routing. - Shih-Ting Lin; Hung-Hsiao Wang; Chia-Yu Kuo; Yolo Chen; Yih-Lang Li (DAC, 2021)

DATC RDF-2021: Design Flow and Beyond ICCAD Special Session Paper. - Jianli Chen; Iris Hui-Ru Jiang; Jinwook Jung; Andrew B. Kahng; Seungwon Kim; Victor N. Kravets; Yih-Lang Li; Ravi Varadarajan; Mingyu Woo (ICCAD, 2021)

Supplemental PDK for ASAP7 Using Synopsys Flow. - Shinichi Nishizawa; Shih-Ting Lin; Yih-Lang Li; Hidetoshi Onodera (IPSJ Trans. Syst. LSI Des. Methodol., 2021)

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Po-Yan Chen; Bing-Ting Ke; Tai-Cheng Lee; I-Ching Tsai; Tai-Wei Kung; Li-Yi Lin; En-Cheng Liu; Yun-Chih Chang; Yih-Lang Li; Mango C.-T. Chao (ISPD, 2022)

Challenges and Approaches in VLSI Routing. - Gracieli Posser; Evangeline F. Y. Young; Stephan Held; Yih-Lang Li; David Z. Pan (ISPD, 2022)

Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. - Li-Wei Chen; Yao-Nien Sui; Tai-Cheng Lee; Yih-Lang Li; Mango C.-T. Chao; I-Ching Tsai; Tai-Wei Kung; En-Cheng Liu; Yun-Chih Chang (ISQED, 2022)

Spatiotemporal Activity Semantics Understanding Based on Foreground Object Segmentation: iCounter Scenario. - Tzu-Wei Yu; Muhammad Atif Sarwar; Yousef-Awwad Daraghmi; Sheng-Hsien Cheng; Tsì-Uí Ik; Yih-Lang Li (IEEE Access, 2022)

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map. - Yih-Lang Li; Shih-Ting Lin; Shinichi Nishizawa; Hong-Yan Su; Ming-Jie Fong; Oscar Chen; Hidetoshi Onodera (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Periodic Physical Activity Information Segmentation, Counting and Recognition From Video. - Sheng-Hsien Cheng; Muhammad Atif Sarwar; Yousef-Awwad Daraghmi; Tsì-Uí Ik; Yih-Lang Li (IEEE Access, 2023)

Skeleton Based Keyframe Detection Framework for Sports Action Analysis: Badminton Smash Case. - Muhammad Atif Sarwar; Yu-Chen Lin; Yousef-Awwad Daraghmi; Tsì-Uí Ik; Yih-Lang Li (IEEE Access, 2023)

Arbitrary-size Multi-layer OARSMT RL Router Trained with Combinatorial Monte-Carlo Tree Search. - Liang-Ting Chen 003; Hung-Ru Kuo; Yih-Lang Li; Mango C.-T. Chao (DAC, 2024)

Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources. - Bing-Xun Song; Ting Xin Lin; Yih-Lang Li (ISPD, 2024)

Scalable CFET Cell Library Synthesis with A DRC-Aware Lookup Table to Optimize Valid Pin Access. - Ting-Wei Lee; Ting Xin Lin; Yih-Lang Li (ISPD, 2025)