A 1.0 GHz clock generator design with a negative delay using a single-shot locking method. - Chua-Chin Wang; Yih-Long Tseng; Rong-Sui Kao (ICECS, 2001)

Dual-polarity high voltage generator design for non-volatile memories. - Chua-Chin Wang; Yih-Long Tseng; Tian-Hau Chen; Ron Hu (ICECS, 2003)

High-PSR bias circuitry for NTSC sync separation. - Chua-Chin Wang; Yih-Long Tseng; Tzung-Je Lee; Ron Hu (ISCAS (1), 2004)

A 4-kB 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches. - Chua-Chin Wang; Yih-Long Tseng; Hon-Yuan Leo; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications. - Chua-Chin Wang; Yih-Long Tseng; Hsien-Chih She; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula. - Chua-Chin Wang; Yih-Long Tseng; Hsien-Chih She; Chih-Chen Li; Ron Hu (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC. - Chua-Chin Wang; Ching-Li Lee; Li-Ping Lin; Yih-Long Tseng (ISCAS (1), 2005)

Low-Power Small-Area Digital I/O Cell. - Chua-Chin Wang; Ching-Li Lee; Yih-Long Tseng; Chiuan-Shian Chen; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

A temperature-insensitive self-recharging circuitry used in DRAMs. - Chua-Chin Wang; Yih-Long Tseng; Chih-Chiang Chiu (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency. - Chua-Chin Wang; Jian-Ming Huang; Yih-Long Tseng; Wun-Ji Lin; Ron Hu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)