A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. - Chun-Hsiung Hung; Meng-Fan Chang; Yih-Shan Yang; Yao-Jen Kuo; Tzu-Neng Lai; Shin-Jang Shen; Jo-Yu Hsu; Shuo-Nan Hung; Hang-Ting Lue; Yen-Hao Shih; Shih-Lin Huang; Ti-Wen Chen; et al. (IEEE J. Solid State Circuits, 2015)