SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2005)

A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. - Kevin Zhang 001; Uddalak Bhattacharya; Zhanping Chen; Fatih Hamzaoglu; Daniel Murray; Narendra Vallepalli; Yih Wang; Bo Zheng; Mark Bohr (IEEE J. Solid State Circuits, 2006)

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; Ian Post; et al. (ISSCC, 2007)

A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (ISSCC, 2008)

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. - Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Tom Coan; Fatih Hamzaoglu; Walid M. Hafez; Chia-Hong Jan; Pramod Kolar; Sarvesh H. Kulkarni; Jie-Feng Lin; Yong-Gee Ng; et al. (IEEE J. Solid State Circuits, 2008)

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (ISSCC, 2009)

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. - Fatih Hamzaoglu; Kevin Zhang 001; Yih Wang; Hong Jo Ahn; Uddalak Bhattacharya; Zhanping Chen; Yong-Gee Ng; Andrei Pavlov; Ken Smits; Mark Bohr (IEEE J. Solid State Circuits, 2009)

Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits. - Muhammad M. Khellah; Nam-Sung Kim; Yibin Ye; Dinesh Somasekhar; Tanay Karnik; Nitin Borkar; Gunjan Pandya; Fatih Hamzaoglu; Tom Coan; Yih Wang; Kevin Zhang 001; Clair Webb; et al. (IEEE J. Solid State Circuits, 2009)

A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. - Hyunwoo Nho; Pramod Kolar; Fatih Hamzaoglu; Yih Wang; Eric Karl; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (ISSCC, 2010)

A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. - Yih Wang; Uddalak Bhattacharya; Fatih Hamzaoglu; Pramod Kolar; Yong-Gee Ng; Liqiong Wei; Ying Zhang; Kevin Zhang 001; Mark Bohr (IEEE J. Solid State Circuits, 2010)

Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. - Fatih Hamzaoglu; Yih Wang; Pramod Kolar; Liqiong Wei; Yong-Gee Ng; Uddalak Bhattacharya; Kevin Zhang 001 (IEEE Des. Test Comput., 2011)

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. - Pramod Kolar; Eric Karl; Uddalak Bhattacharya; Fatih Hamzaoglu; Henry Nho; Yong-Gee Ng; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2011)

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (ISSCC, 2012)

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. - Eric Karl; Yih Wang; Yong-Gee Ng; Zheng Guo; Fatih Hamzaoglu; Mesut Meterelliyoz; John Keane 001; Uddalak Bhattacharya; Kevin Zhang 001; Kaizad Mistry; Mark Bohr (IEEE J. Solid State Circuits, 2013)

13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (ISSCC, 2014)

2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. - Mesut Meterelliyoz; Fuad H. Al-amoody; Umut Arslan; Fatih Hamzaoglu; Luke Hood; Manoj B. Lal; Jeffrey L. Miller; Anand Ramasundar; Dan Soltman; Ifar Wan; Yih Wang; Kevin Zhang 001 (VLSIC, 2014)

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology. - Fatih Hamzaoglu; Umut Arslan; Nabhendra Bisnik; Swaroop Ghosh; Manoj B. Lal; Nick Lindert; Mesut Meterelliyoz; Randy B. Osborne; Joodong Park; Shigeki Tomishima; Yih Wang; Kevin Zhang 001 (IEEE J. Solid State Circuits, 2015)

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. - Qing Dong 001; Mahmut E. Sinangil; Burak Erbagci; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (ISSCC, 2020)

Memory for Data-Centric Computing: A Technology Perspective. - Yih Wang (VLSI-DAT, 2020)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing. - Shaun Chou; Gu-Huan Li; Shawn Chen; Jun-Hao Chang; Wan-Hsueh Cheng; Shao-Ding Wu; Philex Fan; Chia-En Huang; Yu-Der Chih; Yih Wang; Jonathan Chang (VLSI Circuits, 2021)

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. - Mahmut E. Sinangil; Burak Erbagci; Rawan Naous; Kerem Akarvardar; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (IEEE J. Solid State Circuits, 2021)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Mei-Chen Chuang; Rawan Naous; Chao-Kai Chuang; Takeshi Hashizume; Dar Sun; Chia-Fu Lee; Kerem Akarvardar; Saman Adham; Tan-Li Chou; et al. (ISSCC, 2022)

A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. - Nail Etkin Can Akkaya; Gary Chan; Hung-Jen Liao; Yih Wang; Jonathan Chang (VLSI Technology and Circuits, 2022)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs. - Wei-Xiang You; Cheng-Yin Wang; Yih Wang; Tsung-Yung Jonathan Chang; Szuya Sandy Liao (VLSI Technology and Circuits, 2023)

Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). - Masum Hossain; Arijit Raychowdhury; Sanu K. Mathew; Yakun Sophia Shao; Yih Wang (IEEE J. Solid State Circuits, 2023)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C. - Yi-Cheng Huang; Shang-Hsuan Liu; Hsu-Shun Chen; Hsin-Chang Feng; Chih-Feng Li; Chou-Ying Yang; Wei-Keng Chang; Chang-Feng Yang; Chun-Yu Wu; Yen-Cheng Lin; Tsung-Tse Yang; Chih-Yang Chang; et al. (ISSCC, 2024)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Ming-Chieh Huang; Wei Wing Mar; Shankar Kanade; Boris Bai; Aditya Gayatri; Krishna Khairnar; Amy Lai; Yu-Hao Hsu; Hung-Jen Liao; Yih Wang; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)