Scan array solution for testing power and testing time. - Lei Xu 001; Yihe Sun; Hongyi Chen (ITC, 2001)

An Optimizing Search Method of Systolic Array Design. - Ke Jiang; Yihe Sun (IASTED PDCS, 2002)

Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. - He Hu 002; Yihe Sun (Asian Test Symposium, 2003)

A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. - Xingjun Wu; Hongyi Chen; Yihe Sun; Weixin Gai (J. VLSI Signal Process., 2003)

A new register file access architecture for software pipelining in VLIW processors. - Yanjun Zhang; Hu He 001; Yihe Sun (ASP-DAC, 2005)

A Retargetable Compiler of VLIW ASIP for Media Signal Processing. - Zhou Zhixiong; Yang Xu; He Hu 002; Yihe Sun (ESA, 2006)

VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. - Zheng Shen; Hu He 001; Yanjun Zhang; Yihe Sun (IIH-MSP, 2006)

A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. - Zhixiong Zhou; Hu He 001; Yanjun Zhang; Yihe Sun; Adriel Cheng (ASAP, 2007)

Heuristic on a Novel Power Management System Cooperating with Compiler. - Yang Xu; Hu He 001; Zhou Zhixiong; Yanjun Zhang; Yihe Sun (J. Low Power Electron., 2007)

A Video Specific Instruction Set Architecture for ASIP design. - Zheng Shen; Hu He 001; Yanjun Zhang; Yihe Sun (VLSI Design, 2007)

Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. - Adriel Cheng; Cheng-Chew Lim; Yihe Sun; Hu He 001; Zhixiong Zhou; Ting Lei (DELTA, 2008)

Transaction-Aware Network-on-Chip Resource Reservation. - Zheng Li; Changyun Zhu; Li Shang; Robert P. Dick; Yihe Sun (IEEE Comput. Archit. Lett., 2008)

Spectrum: a hybrid nanophotonic-electric on-chip network. - Zheng Li; Dan Fay; Alan Rolf Mickelson; Li Shang; Manish Vachharajani; Dejan Filipovic; Wounjhang Park; Yihe Sun (DAC, 2009)

Latency criticality aware on-chip communication. - Zheng Li; Jie Wu; Li Shang; Robert P. Dick; Yihe Sun (DATE, 2009)

Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. - Zheng Shen; Hu He 001; Yihe Sun (DSD, 2009)

A high-performance low-power nanophotonic on-chip network. - Zheng Li; Jie Wu; Li Shang; Alan Rolf Mickelson; Manish Vachharajani; Dejan Filipovic; Wounjhang Park; Yihe Sun (ISLPED, 2009)

A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. - Yang Xu; Hu He 001; Yihe Sun (J. Low Power Electron., 2009)

A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. - Bo Yu 014; Terrence S. T. Mak; Xiangyu Li; Fei Xia 001; Alexandre Yakovlev; Yihe Sun; Chi-Sang Poon (FPL, 2010)

Accelerating data movement on future chip multi-processors. - Junli Gu; Rakesh Kumar 002; Steven S. Lumetta; Yihe Sun (IFMT, 2010)

Power-efficient variation-aware photonic on-chip network management. - Moustafa Mohamed; Zheng Li; Xi Chen; Li Shang; Alan Rolf Mickelson; Manish Vachharajani; Yihe Sun (ISLPED, 2010)

Global On-Chip Coordination at Light Speed. - Zheng Li; Moustafa Mohamed; Hongyu Zhou; Li Shang; Alan Rolf Mickelson; Dejan Filipovic; Manish Vachharajani; Wounjhang Park; Yihe Sun (IEEE Des. Test Comput., 2010)

Feasibility study for future implantable neural-silicon interface devices. - Allann Al-armaghany; Bo Yu 014; Terrence S. T. Mak; Kin-Fai Tong; Yihe Sun (EMBC, 2011)

Real-time neuronal networks reconstruction using hierarchical systolic arrays. - Bo Yu 014; Terrence S. T. Mak; Yihe Sun; Chi-Sang Poon (EMBC, 2011)

Memory efficient on-line streaming for multichannel spike train analysis. - Bo Yu 014; Terrence S. T. Mak; Leslie Smith; Yihe Sun; Alex Yakovlev; Chi-Sang Poon (EMBC, 2011)

MOPED: Orchestrating interprocess message data on CMPs. - Junli Gu; Steven S. Lumetta; Rakesh Kumar 002; Yihe Sun (HPCA, 2011)

Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. - Bo Yu 014; Terrence S. T. Mak; Xiangyu Li; Fei Xia 001; Alexandre Yakovlev; Yihe Sun; Chi-Sang Poon (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

MOPED: Accelerating Data Communication on Future CMPs. - Junli Gu; Yihe Sun; Steven S. Lumetta; Rakesh Kumar 002 (IEEE Micro, 2011)

Reliability Modeling and Management of Nanophotonic On-Chip Networks. - Zheng Li; Moustafa Mohamed; Xi Chen; Eric Dudley; Ke Meng; Li Shang; Alan Rolf Mickelson; Russ Joseph; Manish Vachharajani; Brian Schwartz; Yihe Sun (IEEE Trans. Very Large Scale Integr. Syst., 2012)

On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. - Bo Yu 014; Rosa H. M. Chan; Terrence S. T. Mak; Yihe Sun; Chi-Sang Poon (IEEE Trans. Biomed. Eng., 2013)

Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. - Jie Wu; Jia Wang 003; Kun Li; Hai Zhou 001; Qin Lv; Li Shang; Yihe Sun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Comprehensive identification of corporate financial risk based on Z-score model and F-score model. - Yihe Sun; Zhiqiang Sun; Xueli He; Yangbin Xiang (ICBAR, 2024)

Low/Middle-Frequency Positive External- Damping Design Under Self-Stability Constraint for Inner Control Loop of Grid-Forming Converters. - Xiaoqiang Li; Chu Chen; Yihe Sun; Hao Cheng (IEEE Trans. Ind. Electron., 2024)